83 lines
3.4 KiB
C
83 lines
3.4 KiB
C
/*
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* Copyright © 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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#ifndef AC_DRM_FOURCC_H
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#define AC_DRM_FOURCC_H
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#ifdef _WIN32
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#include <stdint.h>
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typedef uint64_t __u64;
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#define DRM_FORMAT_MOD_VENDOR_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
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#define fourcc_mod_code(vendor, val) \
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((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
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#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
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#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
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#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
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#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
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#define AMD_FMT_MOD_TILE_VER_GFX9 1
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#define AMD_FMT_MOD_TILE_VER_GFX10 2
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#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
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#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
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#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
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#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
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#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
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#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
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#define AMD_FMT_MOD_DCC_BLOCK_64B 0
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#define AMD_FMT_MOD_DCC_BLOCK_128B 1
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#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
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#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
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#define AMD_FMT_MOD_TILE_SHIFT 8
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#define AMD_FMT_MOD_TILE_MASK 0x1F
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#define AMD_FMT_MOD_DCC_SHIFT 13
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#define AMD_FMT_MOD_DCC_MASK 0x1
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#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
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#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
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#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
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#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
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#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
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#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
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#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
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#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
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#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
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#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
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#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
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#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
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#define AMD_FMT_MOD_RB_SHIFT 30
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#define AMD_FMT_MOD_RB_MASK 0x7
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#define AMD_FMT_MOD_PIPE_SHIFT 33
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#define AMD_FMT_MOD_SET(field, value) \
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((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
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#define AMD_FMT_MOD_GET(field, value) \
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(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
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#else
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#include "drm-uapi/drm_fourcc.h"
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#endif
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#endif /* AC_DRM_FOURCC_H */
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