520 lines
18 KiB
C
520 lines
18 KiB
C
/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
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/*
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* Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include "pipe/p_state.h"
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#include "util/u_string.h"
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#include "util/u_memory.h"
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#include "util/u_inlines.h"
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#include "util/u_pack_color.h"
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#include "freedreno_gmem.h"
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#include "freedreno_context.h"
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#include "freedreno_state.h"
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#include "freedreno_program.h"
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#include "freedreno_resource.h"
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#include "freedreno_zsa.h"
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#include "freedreno_util.h"
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/*
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* GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
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* inside the GPU. All rendering happens to GMEM. Larger render targets
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* are split into tiles that are small enough for the color (and depth and/or
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* stencil, if enabled) buffers to fit within GMEM. Before rendering a tile,
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* if there was not a clear invalidating the previous tile contents, we need
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* to restore the previous tiles contents (system mem -> GMEM), and after all
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* the draw calls, before moving to the next tile, we need to save the tile
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* contents (GMEM -> system mem).
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*
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* The code in this file handles dealing with GMEM and tiling.
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*
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* The structure of the ringbuffer ends up being:
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*
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* +--<---<-- IB ---<---+---<---+---<---<---<--+
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* | | | |
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* v ^ ^ ^
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* ------------------------------------------------------
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* | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
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* ------------------------------------------------------
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* ^
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* |
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* address submitted in issueibcmds
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*
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* Where the per-tile section handles scissor setup, mem2gmem restore (if
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* needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
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* resolve.
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*/
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/* transfer from gmem to system memory (ie. normal RAM) */
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static void
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emit_gmem2mem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base,
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struct pipe_surface *psurf)
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{
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struct fd_resource *rsc = fd_resource(psurf->texture);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
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OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
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A2XX_RB_COLOR_INFO_BASE(base / 1024) |
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A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf->format)));
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OUT_PKT3(ring, CP_SET_CONSTANT, 5);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
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OUT_RING(ring, 0x00000000); /* RB_COPY_CONTROL */
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OUT_RELOC(ring, rsc->bo, 0, 0); /* RB_COPY_DEST_BASE */
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OUT_RING(ring, rsc->pitch >> 5); /* RB_COPY_DEST_PITCH */
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OUT_RING(ring, /* RB_COPY_DEST_INFO */
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A2XX_RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf->format)) |
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A2XX_RB_COPY_DEST_INFO_LINEAR |
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A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
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A2XX_RB_COPY_DEST_INFO_WRITE_RED |
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A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
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A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
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A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
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OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
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OUT_RING(ring, 0x0000000);
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OUT_PKT3(ring, CP_DRAW_INDX, 3);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
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INDEX_SIZE_IGN, IGNORE_VISIBILITY));
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OUT_RING(ring, 3); /* NumIndices */
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}
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static void
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emit_gmem2mem(struct fd_context *ctx, struct fd_ringbuffer *ring,
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uint32_t xoff, uint32_t yoff, uint32_t bin_w, uint32_t bin_h)
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{
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struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
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fd_emit_vertex_bufs(ring, 0x9c, (struct fd_vertex_buf[]) {
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{ .prsc = ctx->solid_vertexbuf, .size = 48 },
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}, 1);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
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OUT_RING(ring, 0);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
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OUT_RING(ring, 0x0000028f);
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fd_program_emit(ring, &ctx->solid_prog);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
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OUT_RING(ring, 0x0000ffff);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
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OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
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OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */
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A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
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A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
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OUT_PKT3(ring, CP_SET_CONSTANT, 3);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
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OUT_RING(ring, xy2d(0, 0)); /* PA_SC_WINDOW_SCISSOR_TL */
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OUT_RING(ring, xy2d(pfb->width, pfb->height)); /* PA_SC_WINDOW_SCISSOR_BR */
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
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OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
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A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
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A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
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A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
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A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
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OUT_RING(ring, 0x00000000);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
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OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET));
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OUT_RING(ring, A2XX_RB_COPY_DEST_OFFSET_X(xoff) |
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A2XX_RB_COPY_DEST_OFFSET_Y(yoff));
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if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
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emit_gmem2mem_surf(ring, 0, bin_w * bin_h, pfb->zsbuf);
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if (ctx->resolve & FD_BUFFER_COLOR)
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emit_gmem2mem_surf(ring, 1, 0, pfb->cbufs[0]);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
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OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
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}
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/* transfer from system memory to gmem */
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static void
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emit_mem2gmem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base,
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struct pipe_surface *psurf)
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{
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struct fd_resource *rsc = fd_resource(psurf->texture);
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uint32_t swiz;
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
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OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
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A2XX_RB_COLOR_INFO_BASE(base) |
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A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf->format)));
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swiz = fd_tex_swiz(psurf->format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
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PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA);
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/* emit fb as a texture: */
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OUT_PKT3(ring, CP_SET_CONSTANT, 7);
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OUT_RING(ring, 0x00010000);
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OUT_RING(ring, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP) |
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A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP) |
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A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) |
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A2XX_SQ_TEX_0_PITCH(rsc->pitch));
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OUT_RELOC(ring, rsc->bo, 0,
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fd_pipe2surface(psurf->format) | 0x800);
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OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) |
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A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1));
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OUT_RING(ring, 0x01000000 | // XXX
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swiz |
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A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
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A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000200);
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OUT_PKT3(ring, CP_DRAW_INDX, 3);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
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INDEX_SIZE_IGN, IGNORE_VISIBILITY));
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OUT_RING(ring, 3); /* NumIndices */
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}
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static void
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emit_mem2gmem(struct fd_context *ctx, struct fd_ringbuffer *ring,
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uint32_t xoff, uint32_t yoff, uint32_t bin_w, uint32_t bin_h)
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{
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struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
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float x0, y0, x1, y1;
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fd_emit_vertex_bufs(ring, 0x9c, (struct fd_vertex_buf[]) {
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{ .prsc = ctx->solid_vertexbuf, .size = 48, .offset = 0x30 },
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{ .prsc = ctx->solid_vertexbuf, .size = 32, .offset = 0x60 },
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}, 2);
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/* write texture coordinates to vertexbuf: */
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x0 = ((float)xoff) / ((float)pfb->width);
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x1 = ((float)xoff + bin_w) / ((float)pfb->width);
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y0 = ((float)yoff) / ((float)pfb->height);
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y1 = ((float)yoff + bin_h) / ((float)pfb->height);
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OUT_PKT3(ring, CP_MEM_WRITE, 9);
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OUT_RELOC(ring, fd_resource(ctx->solid_vertexbuf)->bo, 0x60, 0);
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OUT_RING(ring, fui(x0));
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OUT_RING(ring, fui(y0));
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OUT_RING(ring, fui(x1));
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OUT_RING(ring, fui(y0));
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OUT_RING(ring, fui(x0));
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OUT_RING(ring, fui(y1));
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OUT_RING(ring, fui(x1));
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OUT_RING(ring, fui(y1));
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
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OUT_RING(ring, 0);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
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OUT_RING(ring, 0x0000003b);
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fd_program_emit(ring, &ctx->blit_prog);
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OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
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OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
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OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
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OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
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A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
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A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
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OUT_RING(ring, 0x0000ffff);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
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OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
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A2XX_RB_COLORCONTROL_BLEND_DISABLE |
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A2XX_RB_COLORCONTROL_ROP_CODE(12) |
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A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
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A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
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OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) |
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A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND_DST_PLUS_SRC) |
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A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) |
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A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) |
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A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND_DST_PLUS_SRC) |
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A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO));
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OUT_PKT3(ring, CP_SET_CONSTANT, 3);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
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OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_DISABLE |
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xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */
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OUT_RING(ring, xy2d(bin_w, bin_h)); /* PA_SC_WINDOW_SCISSOR_BR */
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OUT_PKT3(ring, CP_SET_CONSTANT, 5);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
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OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XSCALE */
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OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XOFFSET */
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OUT_RING(ring, fui(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
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OUT_RING(ring, fui((float)bin_h/2.0)); /* PA_CL_VPORT_YOFFSET */
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
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OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT |
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A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT | // XXX check this???
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A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
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A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
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A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
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A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
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OUT_RING(ring, 0x00000000);
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if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
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emit_mem2gmem_surf(ring, 0, bin_w * bin_h, pfb->zsbuf);
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if (ctx->restore & FD_BUFFER_COLOR)
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emit_mem2gmem_surf(ring, 1, 0, pfb->cbufs[0]);
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/* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
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}
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static void
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calculate_tiles(struct fd_context *ctx)
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{
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struct fd_gmem_stateobj *gmem = &ctx->gmem;
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struct pipe_scissor_state *scissor = &ctx->max_scissor;
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uint32_t cpp = util_format_get_blocksize(ctx->framebuffer.cbufs[0]->format);
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uint32_t gmem_size = ctx->screen->gmemsize_bytes;
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uint32_t minx, miny, width, height;
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uint32_t nbins_x = 1, nbins_y = 1;
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uint32_t bin_w, bin_h;
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uint32_t max_width = 992;
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if ((gmem->cpp == cpp) &&
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!memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
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/* everything is up-to-date */
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return;
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}
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minx = scissor->minx & ~31; /* round down to multiple of 32 */
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miny = scissor->miny & ~31;
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width = scissor->maxx - minx;
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height = scissor->maxy - miny;
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// TODO we probably could optimize this a bit if we know that
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// Z or stencil is not enabled for any of the draw calls..
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// if (fd_stencil_enabled(ctx->zsa) || fd_depth_enabled(ctx->zsa)) {
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gmem_size /= 2;
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max_width = 256;
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// }
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bin_w = ALIGN(width, 32);
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bin_h = ALIGN(height, 32);
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/* first, find a bin width that satisfies the maximum width
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* restrictions:
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*/
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while (bin_w > max_width) {
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nbins_x++;
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bin_w = ALIGN(width / nbins_x, 32);
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}
|
|
|
|
/* then find a bin height that satisfies the memory constraints:
|
|
*/
|
|
while ((bin_w * bin_h * cpp) > gmem_size) {
|
|
nbins_y++;
|
|
bin_h = ALIGN(height / nbins_y, 32);
|
|
}
|
|
|
|
DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
|
|
|
|
gmem->scissor = *scissor;
|
|
gmem->cpp = cpp;
|
|
gmem->minx = minx;
|
|
gmem->miny = miny;
|
|
gmem->bin_h = bin_h;
|
|
gmem->bin_w = bin_w;
|
|
gmem->nbins_x = nbins_x;
|
|
gmem->nbins_y = nbins_y;
|
|
gmem->width = width;
|
|
gmem->height = height;
|
|
}
|
|
|
|
void
|
|
fd_gmem_render_tiles(struct pipe_context *pctx)
|
|
{
|
|
struct fd_context *ctx = fd_context(pctx);
|
|
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
|
|
struct fd_gmem_stateobj *gmem = &ctx->gmem;
|
|
struct fd_ringbuffer *ring = ctx->ring;
|
|
enum a2xx_colorformatx colorformatx = fd_pipe2color(pfb->cbufs[0]->format);
|
|
uint32_t i, timestamp, yoff = 0;
|
|
uint32_t reg;
|
|
|
|
calculate_tiles(ctx);
|
|
|
|
DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
|
|
util_format_name(pfb->cbufs[0]->format),
|
|
pfb->zsbuf ? util_format_name(pfb->zsbuf->format) : "none");
|
|
|
|
/* mark the end of the clear/draw cmds before emitting per-tile cmds: */
|
|
fd_ringmarker_mark(ctx->draw_end);
|
|
|
|
/* RB_SURFACE_INFO / RB_DEPTH_INFO can be emitted once per tile pass,
|
|
* but RB_COLOR_INFO gets overwritten by gmem2mem and mem2gmem and so
|
|
* needs to be emitted for each tile:
|
|
*/
|
|
OUT_PKT3(ring, CP_SET_CONSTANT, 4);
|
|
OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO));
|
|
OUT_RING(ring, gmem->bin_w); /* RB_SURFACE_INFO */
|
|
OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
|
|
A2XX_RB_COLOR_INFO_FORMAT(colorformatx));
|
|
reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(ALIGN(gmem->bin_w * gmem->bin_h, 4));
|
|
if (pfb->zsbuf)
|
|
reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
|
|
OUT_RING(ring, reg); /* RB_DEPTH_INFO */
|
|
|
|
yoff= gmem->miny;
|
|
for (i = 0; i < gmem->nbins_y; i++) {
|
|
uint32_t j, xoff = gmem->minx;
|
|
uint32_t bh = gmem->bin_h;
|
|
|
|
/* clip bin height: */
|
|
bh = min(bh, gmem->height - yoff);
|
|
|
|
for (j = 0; j < gmem->nbins_x; j++) {
|
|
uint32_t bw = gmem->bin_w;
|
|
|
|
/* clip bin width: */
|
|
bw = min(bw, gmem->width - xoff);
|
|
|
|
DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
|
|
bh, yoff, bw, xoff);
|
|
|
|
/* setup screen scissor for current tile (same for mem2gmem): */
|
|
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
|
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL));
|
|
OUT_RING(ring, xy2d(0,0)); /* PA_SC_SCREEN_SCISSOR_TL */
|
|
OUT_RING(ring, xy2d(bw, bh)); /* PA_SC_SCREEN_SCISSOR_BR */
|
|
|
|
if (ctx->restore)
|
|
emit_mem2gmem(ctx, ring, xoff, yoff, bw, bh);
|
|
|
|
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
|
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
|
|
OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
|
|
A2XX_RB_COLOR_INFO_FORMAT(colorformatx));
|
|
|
|
/* setup window scissor and offset for current tile (different
|
|
* from mem2gmem):
|
|
*/
|
|
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
|
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
|
|
OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(-xoff) |
|
|
A2XX_PA_SC_WINDOW_OFFSET_Y(-yoff));/* PA_SC_WINDOW_OFFSET */
|
|
|
|
/* emit IB to drawcmds: */
|
|
OUT_IB (ring, ctx->draw_start, ctx->draw_end);
|
|
|
|
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
|
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
|
|
OUT_RING(ring, 0x00000000); /* PA_SC_WINDOW_OFFSET */
|
|
|
|
/* emit gmem2mem to transfer tile back to system memory: */
|
|
emit_gmem2mem(ctx, ring, xoff, yoff, bw, bh);
|
|
|
|
xoff += bw;
|
|
}
|
|
|
|
yoff += bh;
|
|
}
|
|
|
|
/* GPU executes starting from tile cmds, which IB back to draw cmds: */
|
|
fd_ringmarker_flush(ctx->draw_end);
|
|
|
|
/* mark start for next draw cmds: */
|
|
fd_ringmarker_mark(ctx->draw_start);
|
|
|
|
/* update timestamps on render targets: */
|
|
fd_pipe_timestamp(ctx->screen->pipe, ×tamp);
|
|
fd_resource(pfb->cbufs[0]->texture)->timestamp = timestamp;
|
|
if (pfb->zsbuf)
|
|
fd_resource(pfb->zsbuf->texture)->timestamp = timestamp;
|
|
|
|
/* reset maximal bounds: */
|
|
ctx->max_scissor.minx = ctx->max_scissor.miny = ~0;
|
|
ctx->max_scissor.maxx = ctx->max_scissor.maxy = 0;
|
|
|
|
/* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
|
|
* after the draw/clear calls, but executed before, we need to preemptively
|
|
* flag some state as dirty before the first draw/clear call.
|
|
*
|
|
* TODO maybe we need to mark all state as dirty to not worry about state
|
|
* being clobbered by other contexts?
|
|
*/
|
|
ctx->dirty |= FD_DIRTY_ZSA |
|
|
FD_DIRTY_RASTERIZER |
|
|
FD_DIRTY_FRAMEBUFFER |
|
|
FD_DIRTY_SAMPLE_MASK |
|
|
FD_DIRTY_VIEWPORT |
|
|
FD_DIRTY_CONSTBUF |
|
|
FD_DIRTY_PROG |
|
|
FD_DIRTY_SCISSOR |
|
|
/* probably only needed if we need to mem2gmem on the next
|
|
* draw.. but not sure if there is a good way to know?
|
|
*/
|
|
FD_DIRTY_VERTTEX |
|
|
FD_DIRTY_FRAGTEX |
|
|
FD_DIRTY_BLEND;
|
|
}
|