209 lines
8.3 KiB
C
209 lines
8.3 KiB
C
/*
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* Copyright (C) 2018-2020 Collabora, Ltd.
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* Copyright (C) 2019-2020 Icecream95
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "pan_ir.h"
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#include "compiler/nir/nir_builder.h"
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/* Midgard can write all of color, depth and stencil in a single writeout
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* operation, so we merge depth/stencil stores with color stores.
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* If there are no color stores, we add a write to the "depth RT".
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*
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* For Bifrost, we want these combined so we can properly order
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* +ZS_EMIT with respect to +ATEST and +BLEND, as well as combining
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* depth/stencil stores into a single +ZS_EMIT op.
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*/
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/*
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* Get the type to report for a piece of a combined store, given the store it
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* is combining from. If there is no store to render target #0, a dummy <0.0,
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* 0.0, 0.0, 0.0> write is used, so report a matching float32 type.
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*/
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static nir_alu_type
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pan_nir_rt_store_type(nir_intrinsic_instr *store)
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{
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return store ? nir_intrinsic_src_type(store) : nir_type_float32;
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}
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static void
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pan_nir_emit_combined_store(nir_builder *b,
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nir_intrinsic_instr *rt0_store,
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unsigned writeout,
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nir_intrinsic_instr **stores)
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{
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nir_intrinsic_instr *intr = nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_combined_output_pan);
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intr->num_components = rt0_store ? rt0_store->src[0].ssa->num_components : 4;
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if (rt0_store)
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nir_intrinsic_set_base(intr, nir_intrinsic_base(rt0_store));
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nir_intrinsic_set_src_type(intr, pan_nir_rt_store_type(rt0_store));
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nir_intrinsic_set_dest_type(intr, pan_nir_rt_store_type(stores[2]));
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nir_intrinsic_set_component(intr, writeout);
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nir_ssa_def *zero = nir_imm_int(b, 0);
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nir_ssa_def *zero4 = nir_imm_ivec4(b, 0, 0, 0, 0);
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nir_ssa_def *src[] = {
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rt0_store ? rt0_store->src[0].ssa : zero4,
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rt0_store ? rt0_store->src[1].ssa : zero,
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stores[0] ? stores[0]->src[0].ssa : zero,
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stores[1] ? stores[1]->src[0].ssa : zero,
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stores[2] ? stores[2]->src[0].ssa : zero4,
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};
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for (int i = 0; i < ARRAY_SIZE(src); ++i)
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intr->src[i] = nir_src_for_ssa(src[i]);
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nir_builder_instr_insert(b, &intr->instr);
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}
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bool
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pan_nir_lower_zs_store(nir_shader *nir)
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{
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if (nir->info.stage != MESA_SHADER_FRAGMENT)
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return false;
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nir_variable *vars[3] = { NULL };
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nir_foreach_shader_out_variable(var, nir) {
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if (var->data.location == FRAG_RESULT_DEPTH)
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vars[0] = var;
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else if (var->data.location == FRAG_RESULT_STENCIL)
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vars[1] = var;
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else if (var->data.index)
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vars[2] = var;
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}
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if (!vars[0] && !vars[1] && !vars[2])
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return false;
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bool progress = false;
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nir_foreach_function(function, nir) {
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if (!function->impl) continue;
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nir_intrinsic_instr *stores[3] = { NULL };
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nir_foreach_block(block, function->impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic != nir_intrinsic_store_output)
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continue;
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for (unsigned i = 0; i < ARRAY_SIZE(vars); ++i) {
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if (vars[i] && nir_intrinsic_base(intr) == vars[i]->data.driver_location) {
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assert(!stores[i]);
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stores[i] = intr;
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}
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}
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}
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}
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if (!stores[0] && !stores[1] && !stores[2]) continue;
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nir_block *common_block = NULL;
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/* Ensure all stores are in the same block */
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for (unsigned i = 0; i < ARRAY_SIZE(stores); ++i) {
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if (!stores[i])
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continue;
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nir_block *block = stores[i]->instr.block;
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if (common_block)
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assert(common_block == block);
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else
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common_block = block;
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}
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unsigned writeout = 0;
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if (stores[0])
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writeout |= PAN_WRITEOUT_Z;
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if (stores[1])
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writeout |= PAN_WRITEOUT_S;
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if (stores[2])
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writeout |= PAN_WRITEOUT_2;
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bool replaced = false;
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nir_foreach_block(block, function->impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic != nir_intrinsic_store_output)
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continue;
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const nir_variable *var = nir_find_variable_with_driver_location(nir, nir_var_shader_out, nir_intrinsic_base(intr));
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assert(var);
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if (var->data.location < FRAG_RESULT_DATA0)
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continue;
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if (var->data.index)
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continue;
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assert(nir_src_is_const(intr->src[1]) && "no indirect outputs");
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nir_builder b;
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nir_builder_init(&b, function->impl);
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b.cursor = nir_after_block_before_jump(instr->block);
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/* Trying to write depth twice results in the
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* wrong blend shader being executed on
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* Midgard */
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unsigned this_store = PAN_WRITEOUT_C | (replaced ? 0 : writeout);
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pan_nir_emit_combined_store(&b, intr, this_store, stores);
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nir_instr_remove(instr);
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replaced = true;
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}
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}
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/* Insert a store to the depth RT (0xff) if needed */
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if (!replaced) {
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nir_builder b;
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nir_builder_init(&b, function->impl);
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b.cursor = nir_after_block_before_jump(common_block);
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pan_nir_emit_combined_store(&b, NULL, writeout, stores);
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}
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for (unsigned i = 0; i < ARRAY_SIZE(stores); ++i) {
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if (stores[i])
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nir_instr_remove(&stores[i]->instr);
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}
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nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
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progress = true;
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}
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return progress;
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}
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