129 lines
4.1 KiB
C
129 lines
4.1 KiB
C
/*
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* Copyright (C) 2020 Collabora, Ltd.
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* Copyright (C) 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Alyssa Rosenzweig <alyssa@collabora.com>
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* Jason Ekstrand (jason@jlekstrand.net)
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*
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*/
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#include "nir.h"
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#include "pan_ir.h"
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/* Check if a given ALU source is the result of a particular componentwise 1-op
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* ALU source (principally fneg or fabs). If so, return true and rewrite the
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* source to be the argument, respecting swizzles as needed. If not (or it
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* cannot be proven), return false and leave the source untouched.
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*/
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bool
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pan_has_source_mod(nir_alu_src *src, nir_op op)
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{
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if (!src->src.is_ssa || src->src.ssa->parent_instr->type != nir_instr_type_alu)
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return false;
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nir_alu_instr *alu = nir_instr_as_alu(src->src.ssa->parent_instr);
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if (alu->op != op)
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return false;
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/* This only works for unary ops */
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assert(nir_op_infos[op].num_inputs == 1);
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/* If the copied source is not SSA, moving it might not be valid */
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if (!alu->src[0].src.is_ssa)
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return false;
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/* Okay - we've found the modifier we wanted. Let's construct the new ALU
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* src. In a scalar world, this is just psrc, but for vector archs we need
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* to respect the swizzle, so we compose.
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*/
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nir_alu_src nsrc = {
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.src = alu->src[0].src,
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};
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for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i) {
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/* (a o b)(i) = a(b(i)) ... swizzle composition is intense. */
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nsrc.swizzle[i] = alu->src[0].swizzle[src->swizzle[i]];
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}
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*src = nsrc;
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return true;
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}
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/* Check if a given instruction's result will be fed into a
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* componentwise 1-op ALU instruction (principally fsat without
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* swizzles). If so, return true and rewrite the destination. The
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* backend will need to track the new destinations to avoid
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* incorrect double-emits. */
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bool
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pan_has_dest_mod(nir_dest **odest, nir_op op)
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{
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/* This only works for unary ops */
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assert(nir_op_infos[op].num_inputs == 1);
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/* If not SSA, this might not be legal */
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nir_dest *dest = *odest;
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if (!dest->is_ssa)
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return false;
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/* Check the uses. We want a single use, with the op `op` */
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if (!list_is_empty(&dest->ssa.if_uses))
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return false;
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if (!list_is_singular(&dest->ssa.uses))
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return false;
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nir_src *use = list_first_entry(&dest->ssa.uses, nir_src, use_link);
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nir_instr *parent = use->parent_instr;
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/* Check if the op is `op` */
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if (parent->type != nir_instr_type_alu)
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return false;
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nir_alu_instr *alu = nir_instr_as_alu(parent);
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if (alu->op != op)
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return false;
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/* We can't do expansions without a move in the middle */
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unsigned nr_components = nir_dest_num_components(alu->dest.dest);
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if (nir_dest_num_components(*dest) != nr_components)
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return false;
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/* We don't handle swizzles here, so check for the identity */
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for (unsigned i = 0; i < nr_components; ++i) {
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if (alu->src[0].swizzle[i] != i)
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return false;
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}
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if (!alu->dest.dest.is_ssa)
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return false;
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/* Otherwise, we're good */
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*odest = &alu->dest.dest;
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return true;
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}
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