117 lines
4.1 KiB
C
117 lines
4.1 KiB
C
/*
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* Copyright © 2021 Collabora, Ltd.
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* Author: Antonio Caggiano <antonio.caggiano@collabora.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "pan_perf.h"
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#include <pan_perf_metrics.h>
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#include <lib/pan_device.h>
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#include <drm-uapi/panfrost_drm.h>
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#define PAN_COUNTERS_PER_CATEGORY 64
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#define PAN_SHADER_CORE_INDEX 3
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uint32_t
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panfrost_perf_counter_read(const struct panfrost_perf_counter *counter,
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const struct panfrost_perf *perf)
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{
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unsigned offset = perf->category_offset[counter->category_index];
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offset += counter->offset;
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assert(offset < perf->n_counter_values);
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uint32_t ret = perf->counter_values[offset];
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// If counter belongs to shader core, accumulate values for all other cores
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if (counter->category_index == PAN_SHADER_CORE_INDEX) {
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for (uint32_t core = 1; core < perf->dev->core_id_range; ++core) {
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ret += perf->counter_values[offset + PAN_COUNTERS_PER_CATEGORY * core];
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}
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}
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return ret;
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}
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static const struct panfrost_perf_config *
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panfrost_lookup_counters(const char *name)
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{
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for (unsigned i = 0; i < ARRAY_SIZE(panfrost_perf_configs); ++i) {
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if (strcmp(panfrost_perf_configs[i]->name, name) == 0)
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return panfrost_perf_configs[i];
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}
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return NULL;
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}
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void
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panfrost_perf_init(struct panfrost_perf *perf, struct panfrost_device *dev)
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{
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perf->dev = dev;
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if (dev->model == NULL)
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unreachable("Invalid GPU ID");
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perf->cfg = panfrost_lookup_counters(dev->model->performance_counters);
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if (perf->cfg == NULL)
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unreachable("Performance counters missing!");
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// Generally counter blocks are laid out in the following order:
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// Job manager, tiler, one or more L2 caches, and one or more shader cores.
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unsigned l2_slices = panfrost_query_l2_slices(dev);
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uint32_t n_blocks = 2 + l2_slices + dev->core_id_range;
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perf->n_counter_values = PAN_COUNTERS_PER_CATEGORY * n_blocks;
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perf->counter_values = ralloc_array(perf, uint32_t, perf->n_counter_values);
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/* Setup the layout */
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perf->category_offset[0] = PAN_COUNTERS_PER_CATEGORY * 0;
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perf->category_offset[1] = PAN_COUNTERS_PER_CATEGORY * 1;
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perf->category_offset[2] = PAN_COUNTERS_PER_CATEGORY * 2;
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perf->category_offset[3] = PAN_COUNTERS_PER_CATEGORY * (2 + l2_slices);
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}
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static int
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panfrost_perf_query(struct panfrost_perf *perf, uint32_t enable)
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{
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struct drm_panfrost_perfcnt_enable perfcnt_enable = {enable, 0};
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return drmIoctl(perf->dev->fd, DRM_IOCTL_PANFROST_PERFCNT_ENABLE, &perfcnt_enable);
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}
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int
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panfrost_perf_enable(struct panfrost_perf *perf)
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{
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return panfrost_perf_query(perf, 1 /* enable */);
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}
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int
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panfrost_perf_disable(struct panfrost_perf *perf)
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{
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return panfrost_perf_query(perf, 0 /* disable */);
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}
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int
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panfrost_perf_dump(struct panfrost_perf *perf)
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{
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// Dump performance counter values to the memory buffer pointed to by counter_values
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struct drm_panfrost_perfcnt_dump perfcnt_dump = {(uint64_t)(uintptr_t)perf->counter_values};
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return drmIoctl(perf->dev->fd, DRM_IOCTL_PANFROST_PERFCNT_DUMP, &perfcnt_dump);
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}
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