355 lines
11 KiB
C
355 lines
11 KiB
C
/*
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* Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
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* Copyright (C) 2019-2020 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <math.h>
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#include "util/bitscan.h"
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#include "util/half_float.h"
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#include "compiler.h"
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#include "helpers.h"
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#include "midgard_ops.h"
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/* Pretty printer for Midgard IR, for use debugging compiler-internal
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* passes like register allocation. The output superficially resembles
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* Midgard assembly, with the exception that unit information and such is
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* (normally) omitted, and generic indices are usually used instead of
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* registers */
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static void
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mir_print_index(int source)
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{
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if (source == ~0) {
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printf("_");
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return;
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}
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if (source >= SSA_FIXED_MINIMUM) {
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/* Specific register */
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int reg = SSA_REG_FROM_FIXED(source);
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/* TODO: Moving threshold */
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if (reg > 16 && reg < 24)
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printf("U%d", 23 - reg);
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else
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printf("R%d", reg);
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} else if (source & PAN_IS_REG) {
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printf("r%d", source >> 1);
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} else {
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printf("%d", source >> 1);
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}
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}
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static const char components[16] = "xyzwefghijklmnop";
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static void
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mir_print_mask(unsigned mask)
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{
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printf(".");
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for (unsigned i = 0; i < 16; ++i) {
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if (mask & (1 << i))
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putchar(components[i]);
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}
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}
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/*
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* Print a swizzle. We only print the components enabled by the corresponding
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* writemask, as the other components will be ignored by the hardware and so
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* don't matter.
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*/
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static void
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mir_print_swizzle(unsigned mask, unsigned *swizzle)
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{
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printf(".");
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for (unsigned i = 0; i < 16; ++i) {
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if (mask & BITFIELD_BIT(i)) {
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unsigned C = swizzle[i];
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putchar(components[C]);
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}
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}
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}
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static const char *
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mir_get_unit(unsigned unit)
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{
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switch (unit) {
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case ALU_ENAB_VEC_MUL:
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return "vmul";
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case ALU_ENAB_SCAL_ADD:
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return "sadd";
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case ALU_ENAB_VEC_ADD:
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return "vadd";
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case ALU_ENAB_SCAL_MUL:
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return "smul";
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case ALU_ENAB_VEC_LUT:
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return "lut";
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case ALU_ENAB_BR_COMPACT:
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return "br";
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case ALU_ENAB_BRANCH:
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return "brx";
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default:
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return "???";
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}
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}
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static void
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mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
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{
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assert(src_idx <= 1);
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unsigned base_size = max_bitsize_for_alu(ins);
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unsigned sz = nir_alu_type_get_type_size(ins->src_types[src_idx]);
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bool half = (sz == (base_size >> 1));
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unsigned mod = mir_pack_mod(ins, src_idx, false);
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unsigned *swizzle = ins->swizzle[src_idx];
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midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins));
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unsigned comp_mask = effective_writemask(ins->op, ins->mask);
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unsigned num_comp = util_bitcount(comp_mask);
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unsigned max_comp = mir_components_for_type(ins->dest_type);
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bool first = true;
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printf("#");
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if (num_comp > 1)
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printf("vec%d(", num_comp);
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for (unsigned comp = 0; comp < max_comp; comp++) {
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if (!(comp_mask & (1 << comp)))
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continue;
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if (first)
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first = false;
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else
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printf(", ");
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mir_print_constant_component(stdout, &ins->constants,
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swizzle[comp], reg_mode,
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half, mod, ins->op);
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}
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if (num_comp > 1)
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printf(")");
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}
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static void
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mir_print_src(midgard_instruction *ins, unsigned c)
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{
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mir_print_index(ins->src[c]);
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if (ins->src[c] != ~0 && ins->src_types[c] != nir_type_invalid) {
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pan_print_alu_type(ins->src_types[c], stdout);
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mir_print_swizzle(ins->mask, ins->swizzle[c]);
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}
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}
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void
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mir_print_instruction(midgard_instruction *ins)
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{
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printf("\t");
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if (midgard_is_branch_unit(ins->unit)) {
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const char *branch_target_names[] = {
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"goto", "break", "continue", "discard"
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};
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printf("%s.", mir_get_unit(ins->unit));
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if (ins->branch.target_type == TARGET_DISCARD)
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printf("discard.");
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else if (ins->writeout)
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printf("write.");
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else if (ins->unit == ALU_ENAB_BR_COMPACT &&
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!ins->branch.conditional)
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printf("uncond.");
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else
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printf("cond.");
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if (!ins->branch.conditional)
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printf("always");
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else if (ins->branch.invert_conditional)
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printf("false");
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else
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printf("true");
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if (ins->writeout) {
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printf(" (c: ");
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mir_print_src(ins, 0);
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printf(", z: ");
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mir_print_src(ins, 2);
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printf(", s: ");
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mir_print_src(ins, 3);
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printf(")");
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}
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if (ins->branch.target_type != TARGET_DISCARD)
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printf(" %s -> block(%d)\n",
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ins->branch.target_type < 4 ?
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branch_target_names[ins->branch.target_type] : "??",
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ins->branch.target_block);
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return;
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}
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switch (ins->type) {
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case TAG_ALU_4: {
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midgard_alu_op op = ins->op;
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const char *name = alu_opcode_props[op].name;
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if (ins->unit)
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printf("%s.", mir_get_unit(ins->unit));
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printf("%s", name ? name : "??");
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if (!(midgard_is_integer_out_op(ins->op) && ins->outmod == midgard_outmod_keeplo)) {
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mir_print_outmod(stdout, ins->outmod, midgard_is_integer_out_op(ins->op));
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}
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break;
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}
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case TAG_LOAD_STORE_4: {
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midgard_load_store_op op = ins->op;
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const char *name = load_store_opcode_props[op].name;
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assert(name);
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printf("%s", name);
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break;
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}
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case TAG_TEXTURE_4: {
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printf("TEX");
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if (ins->helper_terminate)
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printf(".terminate");
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if (ins->helper_execute)
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printf(".execute");
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break;
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}
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default:
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assert(0);
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}
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if (ins->compact_branch && ins->branch.invert_conditional)
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printf(".not");
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printf(" ");
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mir_print_index(ins->dest);
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if (ins->dest != ~0) {
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pan_print_alu_type(ins->dest_type, stdout);
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mir_print_mask(ins->mask);
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}
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printf(", ");
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/* Only ALU can have an embedded constant, r26 as read on load/store is
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* something else entirely */
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bool is_alu = ins->type == TAG_ALU_4;
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unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
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if (is_alu && alu_opcode_props[ins->op].props & QUIRK_FLIPPED_R24) {
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/* Moves (indicated by QUIRK_FLIPPED_R24) are 1-src, with their
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* one source in the second slot
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*/
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assert(ins->src[0] == ~0);
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} else {
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if (ins->src[0] == r_constant && is_alu)
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mir_print_embedded_constant(ins, 0);
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else
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mir_print_src(ins, 0);
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printf(", ");
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}
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if (ins->has_inline_constant)
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printf("#%d", ins->inline_constant);
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else if (ins->src[1] == r_constant && is_alu)
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mir_print_embedded_constant(ins, 1);
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else
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mir_print_src(ins, 1);
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if (is_alu) {
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/* ALU ops are all 2-src */
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assert(ins->src[2] == ~0);
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assert(ins->src[3] == ~0);
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} else {
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for (unsigned c = 2; c <= 3; ++c) {
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printf(", ");
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mir_print_src(ins, c);
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}
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}
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if (ins->no_spill)
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printf(" /* no spill */");
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printf("\n");
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}
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/* Dumps MIR for a block or entire shader respective */
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void
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mir_print_block(midgard_block *block)
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{
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printf("block%u: {\n", block->base.name);
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if (block->scheduled) {
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mir_foreach_bundle_in_block(block, bundle) {
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for (unsigned i = 0; i < bundle->instruction_count; ++i)
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mir_print_instruction(bundle->instructions[i]);
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printf("\n");
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}
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} else {
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mir_foreach_instr_in_block(block, ins) {
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mir_print_instruction(ins);
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}
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}
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printf("}");
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if (block->base.successors[0]) {
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printf(" -> ");
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pan_foreach_successor((&block->base), succ)
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printf(" block%u ", succ->name);
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}
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printf(" from { ");
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mir_foreach_predecessor(block, pred)
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printf("block%u ", pred->base.name);
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printf("}");
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printf("\n\n");
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}
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void
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mir_print_shader(compiler_context *ctx)
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{
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mir_foreach_block(ctx, block) {
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mir_print_block((midgard_block *) block);
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}
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}
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