442 lines
14 KiB
C
442 lines
14 KiB
C
/* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
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* Copyright (C) 2019-2020 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef __MDG_HELPERS_H
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#define __MDG_HELPERS_H
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#include "util/macros.h"
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#include <stdio.h>
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#include <string.h>
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#define OP_IS_LOAD_VARY_F(op) (\
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op == midgard_op_ld_vary_16 || \
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op == midgard_op_ld_vary_32 \
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)
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#define OP_IS_PROJECTION(op) ( \
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op == midgard_op_ldst_perspective_div_y || \
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op == midgard_op_ldst_perspective_div_z || \
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op == midgard_op_ldst_perspective_div_w \
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)
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#define OP_IS_VEC4_ONLY(op) ( \
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OP_IS_PROJECTION(op) || \
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op == midgard_op_ld_cubemap_coords \
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)
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#define OP_IS_MOVE(op) ( \
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(op >= midgard_alu_op_fmov && op <= midgard_alu_op_fmov_rtp) || \
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op == midgard_alu_op_imov \
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)
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#define OP_IS_UBO_READ(op) ( \
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op >= midgard_op_ld_ubo_u8 && \
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op <= midgard_op_ld_ubo_128_bswap8 \
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)
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#define OP_IS_CSEL_V(op) ( \
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op == midgard_alu_op_icsel_v || \
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op == midgard_alu_op_fcsel_v \
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)
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#define OP_IS_CSEL(op) ( \
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OP_IS_CSEL_V(op) || \
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op == midgard_alu_op_icsel || \
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op == midgard_alu_op_fcsel \
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)
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#define OP_IS_UNSIGNED_CMP(op) ( \
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op == midgard_alu_op_ult || \
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op == midgard_alu_op_ule \
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)
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#define OP_IS_INTEGER_CMP(op) ( \
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op == midgard_alu_op_ieq || \
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op == midgard_alu_op_ine || \
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op == midgard_alu_op_ilt || \
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op == midgard_alu_op_ile || \
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OP_IS_UNSIGNED_CMP(op) \
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)
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#define OP_IS_COMMON_STORE(op) ( \
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op >= midgard_op_st_u8 && \
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op <= midgard_op_st_128_bswap8 \
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)
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#define OP_IS_IMAGE(op) ( \
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(op >= midgard_op_ld_image_32f && op <= midgard_op_ld_image_32i) || \
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(op >= midgard_op_st_image_32f && op <= midgard_op_st_image_32i) || \
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op == midgard_op_lea_image \
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)
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#define OP_IS_SPECIAL(op) ( \
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(op >= midgard_op_ld_special_32f && op <= midgard_op_ld_special_32i) || \
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(op >= midgard_op_st_special_32f && op <= midgard_op_st_special_32i) \
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)
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#define OP_IS_PACK_COLOUR(op) ( \
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(op >= midgard_op_pack_colour_f32 && op <= midgard_op_pack_colour_s32) \
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)
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#define OP_IS_UNPACK_COLOUR(op) ( \
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(op >= midgard_op_unpack_colour_f32 && op <= midgard_op_unpack_colour_s32) \
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)
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/* Instructions that are on the load/store unit but don't access memory */
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#define OP_IS_REG2REG_LDST(op) ( \
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op >= midgard_op_unpack_colour_f32 && \
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op <= midgard_op_ldst_perspective_div_w \
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)
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/* ALU control words are single bit fields with a lot of space */
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#define ALU_ENAB_VEC_MUL (1 << 17)
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#define ALU_ENAB_SCAL_ADD (1 << 19)
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#define ALU_ENAB_VEC_ADD (1 << 21)
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#define ALU_ENAB_SCAL_MUL (1 << 23)
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#define ALU_ENAB_VEC_LUT (1 << 25)
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#define ALU_ENAB_BR_COMPACT (1 << 26)
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#define ALU_ENAB_BRANCH (1 << 27)
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/* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
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/* Denotes an opcode that takes a vector input with a fixed-number of
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* channels, but outputs to only a single output channel, like dot products.
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* For these, to determine the effective mask, this quirk can be set. We have
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* an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
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* sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
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* make sense (since then why are we quirked?), so that corresponds to "no
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* count set" */
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#define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
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#define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
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/* For instructions that take a single argument, normally the first argument
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* slot is used for the argument and the second slot is a dummy #0 constant.
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* However, there are exceptions: instructions like fmov store their argument
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* in the _second_ slot and store a dummy r24 in the first slot, designated by
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* QUIRK_FLIPPED_R24 */
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#define QUIRK_FLIPPED_R24 (1 << 2)
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/* Is the op commutative? */
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#define OP_COMMUTES (1 << 3)
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/* Does the op convert types between int- and float- space (i2f/f2u/etc) */
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#define OP_TYPE_CONVERT (1 << 4)
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/* Is this opcode the first in a f2x (rte, rtz, rtn, rtp) sequence? If so,
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* takes a roundmode argument in the IR. This has the semantic of rounding the
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* source (it's all fused in), which is why it doesn't necessarily make sense
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* for i2f (though folding there might be necessary for OpenCL reasons). Comes
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* up in format conversion, i.e. f2u_rte */
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#define MIDGARD_ROUNDS (1 << 5)
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/* Vector-independant shorthands for the above; these numbers are arbitrary and
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* not from the ISA. Convert to the above with unit_enum_to_midgard */
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#define UNIT_MUL 0
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#define UNIT_ADD 1
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#define UNIT_LUT 2
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#define IS_ALU(tag) (tag >= TAG_ALU_4)
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/* Special register aliases */
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#define MAX_WORK_REGISTERS 16
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/* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
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#define REGISTER_UNIFORMS 24
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/* r24 and r25 are special registers that only exist during the pipeline,
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* by using them when we don't care about the register we skip a roundtrip
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* to the register file. */
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#define REGISTER_UNUSED 24
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#define REGISTER_CONSTANT 26
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#define REGISTER_LDST_BASE 26
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#define REGISTER_TEXTURE_BASE 28
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#define REGISTER_SELECT 31
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/* The following registers are read-only */
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/* XY is Program Counter, ZW is Stack Pointer */
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#define REGISTER_LDST_PC_SP 2
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/* XY is Thread Local Storage pointer, ZW is Workgroup Local Storage pointer */
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#define REGISTER_LDST_LOCAL_STORAGE_PTR 3
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#define REGISTER_LDST_LOCAL_THREAD_ID 4
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#define REGISTER_LDST_GROUP_ID 5
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#define REGISTER_LDST_GLOBAL_THREAD_ID 6
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/* This register is always zeroed when read. */
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#define REGISTER_LDST_ZERO 7
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/* SSA helper aliases to mimic the registers. */
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#define SSA_FIXED_SHIFT 24
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#define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
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#define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
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#define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
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#define COMPONENT_X 0x0
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#define COMPONENT_Y 0x1
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#define COMPONENT_Z 0x2
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#define COMPONENT_W 0x3
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#define SWIZZLE_IDENTITY { \
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 } \
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}
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#define SWIZZLE_IDENTITY_4 { \
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{ 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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}
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static inline unsigned
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mask_of(unsigned nr_comp)
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{
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return (1 << nr_comp) - 1;
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}
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/* See ISA notes */
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#define LDST_NOP (3)
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/* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
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* implemented on some subset of these units (or occassionally all of them).
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* This table encodes a bit mask of valid units for each opcode, so the
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* scheduler can figure where to plonk the instruction. */
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/* Shorthands for each unit */
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#define UNIT_VMUL ALU_ENAB_VEC_MUL
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#define UNIT_SADD ALU_ENAB_SCAL_ADD
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#define UNIT_VADD ALU_ENAB_VEC_ADD
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#define UNIT_SMUL ALU_ENAB_SCAL_MUL
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#define UNIT_VLUT ALU_ENAB_VEC_LUT
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/* Shorthands for usual combinations of units */
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#define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
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#define UNITS_ADD (UNIT_VADD | UNIT_SADD)
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#define UNITS_MOST (UNITS_MUL | UNITS_ADD)
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#define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
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#define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
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#define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
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#define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
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struct mir_op_props {
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const char *name;
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unsigned props;
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};
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/* For load/store */
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struct mir_ldst_op_props {
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const char *name;
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unsigned props;
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};
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struct mir_tex_op_props {
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const char *name;
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unsigned props;
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};
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struct mir_tag_props {
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const char *name;
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unsigned size;
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};
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/* Lower 2-bits are a midgard_reg_mode */
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#define GET_LDST_SIZE(c) (c & 3)
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/* Store (so the primary register is a source, not a destination */
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#define LDST_STORE (1 << 2)
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/* Mask has special meaning and should not be manipulated directly */
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#define LDST_SPECIAL_MASK (1 << 3)
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/* Non-store operation has side effects and should not be eliminated even if
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* its mask is 0 */
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#define LDST_SIDE_FX (1 << 4)
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/* Computes an address according to indirects/zext/shift/etc */
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#define LDST_ADDRESS (1 << 5)
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/* Some fields such swizzle and address have special meanings */
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#define LDST_ATOMIC (1 << 6)
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/* Operates on attributes/varyings (including images) */
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#define LDST_ATTRIB (1 << 7)
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/* This file is common, so don't define the tables themselves. #include
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* midgard_op.h if you need that, or edit midgard_ops.c directly */
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/* Duplicate bits to convert a per-component to duplicated 8-bit format,
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* which is used for vector units */
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static inline unsigned
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expand_writemask(unsigned mask, unsigned log2_channels)
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{
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unsigned o = 0;
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unsigned factor = 8 >> log2_channels;
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unsigned expanded = (1 << factor) - 1;
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for (unsigned i = 0; i < (1 << log2_channels); ++i)
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if (mask & (1 << i))
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o |= (expanded << (factor * i));
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return o;
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}
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/* Coerce structs to integer */
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static inline unsigned
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vector_alu_srco_unsigned(midgard_vector_alu_src src)
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{
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unsigned u;
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memcpy(&u, &src, sizeof(src));
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return u;
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}
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static inline midgard_vector_alu_src
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vector_alu_from_unsigned(unsigned u)
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{
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midgard_vector_alu_src s;
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memcpy(&s, &u, sizeof(s));
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return s;
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}
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static inline void
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mir_compose_swizzle(unsigned *left, unsigned *right, unsigned *final_out)
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{
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unsigned out[16];
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for (unsigned c = 0; c < 16; ++c)
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out[c] = right[left[c]];
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memcpy(final_out, out, sizeof(out));
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}
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/* Checks for an xyzw.. swizzle, given a mask */
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static inline bool
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mir_is_simple_swizzle(unsigned *swizzle, unsigned mask)
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{
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for (unsigned i = 0; i < 16; ++i) {
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if (!(mask & (1 << i))) continue;
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if (swizzle[i] != i)
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return false;
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}
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return true;
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}
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/* Packs a load/store argument */
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static inline uint8_t
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midgard_ldst_comp(unsigned reg, unsigned component, unsigned size)
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{
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assert((reg & ~1) == 0);
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assert(size == 16 || size == 32 || size == 64);
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/* Shift so everything is in terms of 32-bit units */
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if (size == 64) {
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assert(component < 2);
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component <<= 1;
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} else if (size == 16) {
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assert((component & 1) == 0);
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component >>= 1;
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}
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return component;
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}
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/* Packs/unpacks a ubo index immediate. The unpack must be defined here so it
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* can be used with the disassembler, which need not be linked with the main
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* compiler.
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*/
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void midgard_pack_ubo_index_imm(midgard_load_store_word *word, unsigned index);
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static inline unsigned
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midgard_unpack_ubo_index_imm(midgard_load_store_word word)
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{
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unsigned ubo = word.arg_comp |
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(word.arg_reg << 2) |
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(word.bitsize_toggle << 5) |
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(word.index_format << 6);
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return ubo;
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}
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/* Packs/unpacks varying parameters.
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* FIXME: IMPORTANT: We currently handle varying mode weirdly, by passing all
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* parameters via an offset and using REGISTER_LDST_ZERO as base. This works
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* for most parameters, but does not allow us to encode/decode direct sample
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* position. */
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void midgard_pack_varying_params(midgard_load_store_word *word, midgard_varying_params p);
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midgard_varying_params midgard_unpack_varying_params(midgard_load_store_word word);
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/* Load/store ops' displacement helpers.
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* This is useful because different types of load/store ops have different
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* displacement bitsize. */
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#define UNPACK_LDST_ATTRIB_OFS(a) ((a) >> 9)
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#define UNPACK_LDST_VERTEX_OFS(a) util_sign_extend((a) & 0x1FF, 9)
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#define UNPACK_LDST_SELECTOR_OFS(a) ((a) >> 9)
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#define UNPACK_LDST_UBO_OFS(a) ((a) >> 2)
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#define UNPACK_LDST_MEM_OFS(a) ((a))
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#define PACK_LDST_ATTRIB_OFS(a) ((a) << 9)
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#define PACK_LDST_VERTEX_OFS(a) ((a) & 0x1FF)
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#define PACK_LDST_SELECTOR_OFS(a) ((a) << 9)
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#define PACK_LDST_UBO_OFS(a) ((a) << 2)
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#define PACK_LDST_MEM_OFS(a) ((a))
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static inline bool
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midgard_is_branch_unit(unsigned unit)
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{
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return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
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}
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/* Packs ALU mod argument */
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struct midgard_instruction;
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unsigned mir_pack_mod(struct midgard_instruction *ins, unsigned i, bool scalar);
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void
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mir_print_constant_component(FILE *fp, const midgard_constants *consts,
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unsigned c, midgard_reg_mode reg_mode, bool half,
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unsigned mod, midgard_alu_op op);
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void
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mir_print_outmod(FILE *fp, unsigned outmod, bool is_int);
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#endif
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