mesa/src/intel/tools
Kenneth Graunke 72e9843991 intel/compiler: Introduce a new brw_isa_info structure
This structure will contain the opcode mapping tables in the next
commit.  For now, this is the mechanical change to plumb it into all
the necessary places, and it continues simply holding devinfo.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
..
imgui
tests
aub_mem.c
aub_mem.h
aub_read.c intel/tools: fix 32-bit build 2022-05-24 18:27:32 +00:00
aub_read.h intel/tools/aubinator: add support for 2 "new" subopcodes 2022-05-24 08:03:44 +00:00
aub_write.c intel/tools: drop wrappers around mmio regs macros 2022-05-24 08:03:44 +00:00
aub_write.h
aubinator.c intel/compiler: Introduce a new brw_isa_info structure 2022-06-30 23:46:35 +00:00
aubinator_error_decode.c intel/compiler: Introduce a new brw_isa_info structure 2022-06-30 23:46:35 +00:00
aubinator_viewer.cpp intel/compiler: Introduce a new brw_isa_info structure 2022-06-30 23:46:35 +00:00
aubinator_viewer.h
aubinator_viewer_decoder.cpp
aubinator_viewer_urb.h
error2aub.c
gfx8_context.h
gfx10_context.h
i965_asm.c intel/compiler: Introduce a new brw_isa_info structure 2022-06-30 23:46:35 +00:00
i965_asm.h
i965_disasm.c intel/compiler: Introduce a new brw_isa_info structure 2022-06-30 23:46:35 +00:00
i965_gram.y
i965_lex.l
intel_aub.h
intel_context.h intel/tools: add macros for gfx12+ variant of VCSUNIT0 2022-05-24 08:03:45 +00:00
intel_dump_gpu.c intel: fix typos found by codespell 2022-06-27 10:20:55 +00:00
intel_dump_gpu.in
intel_noop_drm_shim.c drm-shim: Better mmap offsets 2022-05-02 19:50:33 +00:00
intel_sanitize_gpu.c intel: fix typos found by codespell 2022-06-27 10:20:55 +00:00
intel_sanitize_gpu.in
intel_stub_gpu.in
meson.build Use proper types for meson objects 2022-04-18 13:03:08 +03:00