1054 lines
32 KiB
C++
1054 lines
32 KiB
C++
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Based on test_fs_cmod_propagation.cpp
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*/
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#include <gtest/gtest.h>
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#include "brw_vec4.h"
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#include "brw_vec4_builder.h"
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#include "brw_cfg.h"
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#include "program/program.h"
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using namespace brw;
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class cmod_propagation_vec4_test : public ::testing::Test {
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virtual void SetUp();
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virtual void TearDown();
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public:
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struct brw_compiler *compiler;
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struct intel_device_info *devinfo;
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void *ctx;
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struct gl_shader_program *shader_prog;
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struct brw_vue_prog_data *prog_data;
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vec4_visitor *v;
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};
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class cmod_propagation_vec4_visitor : public vec4_visitor
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{
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public:
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cmod_propagation_vec4_visitor(struct brw_compiler *compiler,
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void *mem_ctx,
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nir_shader *shader,
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struct brw_vue_prog_data *prog_data)
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: vec4_visitor(compiler, NULL, NULL, prog_data, shader, mem_ctx,
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false, false)
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{
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prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
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}
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protected:
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/* Dummy implementation for pure virtual methods */
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virtual dst_reg *make_reg_for_system_value(int /* location */)
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{
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unreachable("Not reached");
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}
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virtual void setup_payload()
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{
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unreachable("Not reached");
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}
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virtual void emit_prolog()
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{
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unreachable("Not reached");
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}
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virtual void emit_program_code()
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{
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unreachable("Not reached");
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}
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virtual void emit_thread_end()
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{
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unreachable("Not reached");
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}
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virtual void emit_urb_write_header(int /* mrf */)
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{
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unreachable("Not reached");
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}
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virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */)
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{
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unreachable("Not reached");
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}
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};
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void cmod_propagation_vec4_test::SetUp()
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{
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ctx = ralloc_context(NULL);
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compiler = rzalloc(ctx, struct brw_compiler);
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devinfo = rzalloc(ctx, struct intel_device_info);
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compiler->devinfo = devinfo;
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prog_data = ralloc(ctx, struct brw_vue_prog_data);
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nir_shader *shader =
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nir_shader_create(ctx, MESA_SHADER_VERTEX, NULL, NULL);
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v = new cmod_propagation_vec4_visitor(compiler, ctx, shader, prog_data);
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devinfo->ver = 7;
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devinfo->verx10 = devinfo->ver * 10;
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}
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void cmod_propagation_vec4_test::TearDown()
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{
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delete v;
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v = NULL;
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ralloc_free(ctx);
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ctx = NULL;
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}
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static vec4_instruction *
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instruction(bblock_t *block, int num)
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{
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vec4_instruction *inst = (vec4_instruction *)block->start();
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for (int i = 0; i < num; i++) {
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inst = (vec4_instruction *)inst->next;
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}
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return inst;
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}
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static bool
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cmod_propagation(vec4_visitor *v)
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{
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const bool print = getenv("TEST_DEBUG");
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if (print) {
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fprintf(stderr, "= Before =\n");
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v->dump_instructions();
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}
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bool ret = v->opt_cmod_propagation();
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if (print) {
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fprintf(stderr, "\n= After =\n");
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v->dump_instructions();
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}
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return ret;
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}
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TEST_F(cmod_propagation_vec4_test, basic)
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{
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const vec4_builder bld = vec4_builder(v).at_end();
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dst_reg dest = dst_reg(v, glsl_type::float_type);
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src_reg src0 = src_reg(v, glsl_type::float_type);
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src_reg src1 = src_reg(v, glsl_type::float_type);
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src_reg zero(brw_imm_f(0.0f));
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dst_reg dest_null = bld.null_reg_f();
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dest_null.writemask = WRITEMASK_X;
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bld.ADD(dest, src0, src1);
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bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE);
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/* = Before =
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*
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* 0: add dest.x src0.xxxx src1.xxxx
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* 1: cmp.ge.f0 null.x dest.xxxx 0.0f
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*
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* = After =
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* 0: add.ge.f0 dest.x src0.xxxx src1.xxxx
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_TRUE(cmod_propagation(v));
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(0, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
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}
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TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask)
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{
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const vec4_builder bld = vec4_builder(v).at_end();
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dst_reg dest = dst_reg(v, glsl_type::float_type);
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src_reg src0 = src_reg(v, glsl_type::float_type);
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src_reg src1 = src_reg(v, glsl_type::float_type);
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src_reg zero(brw_imm_f(0.0f));
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dst_reg dest_null = bld.null_reg_f();
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bld.ADD(dest, src0, src1);
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bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE);
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/* = Before =
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*
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* 0: add dest.x src0 src1
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* 1: cmp.ge.f0 null.xyzw dest 0.0f
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(1, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
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}
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TEST_F(cmod_propagation_vec4_test, andz_one)
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{
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const vec4_builder bld = vec4_builder(v).at_end();
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dst_reg dest = dst_reg(v, glsl_type::int_type);
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src_reg src0 = src_reg(v, glsl_type::float_type);
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src_reg zero(brw_imm_f(0.0f));
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src_reg one(brw_imm_d(1));
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bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L);
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set_condmod(BRW_CONDITIONAL_Z,
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bld.AND(bld.null_reg_d(), src_reg(dest), one));
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/* = Before =
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* 0: cmp.l.f0 dest:F src0:F 0F
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* 1: and.z.f0 null:D dest:D 1D
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(1, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
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EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod);
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}
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TEST_F(cmod_propagation_vec4_test, non_cmod_instruction)
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{
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const vec4_builder bld = vec4_builder(v).at_end();
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dst_reg dest = dst_reg(v, glsl_type::uint_type);
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src_reg src0 = src_reg(v, glsl_type::uint_type);
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src_reg zero(brw_imm_ud(0u));
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bld.FBL(dest, src0);
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bld.CMP(bld.null_reg_ud(), src_reg(dest), zero, BRW_CONDITIONAL_GE);
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/* = Before =
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*
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* 0: fbl dest src0
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* 1: cmp.ge.f0 null dest 0u
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(1, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_FBL, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
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}
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TEST_F(cmod_propagation_vec4_test, intervening_flag_write)
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{
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const vec4_builder bld = vec4_builder(v).at_end();
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dst_reg dest = dst_reg(v, glsl_type::float_type);
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src_reg src0 = src_reg(v, glsl_type::float_type);
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src_reg src1 = src_reg(v, glsl_type::float_type);
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src_reg src2 = src_reg(v, glsl_type::float_type);
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src_reg zero(brw_imm_f(0.0f));
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bld.ADD(dest, src0, src1);
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bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE);
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bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_GE);
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/* = Before =
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*
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* 0: add dest src0 src1
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* 1: cmp.ge.f0 null src2 0.0f
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* 2: cmp.ge.f0 null dest 0.0f
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
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}
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TEST_F(cmod_propagation_vec4_test, intervening_flag_read)
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{
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const vec4_builder bld = vec4_builder(v).at_end();
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dst_reg dest0 = dst_reg(v, glsl_type::float_type);
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dst_reg dest1 = dst_reg(v, glsl_type::float_type);
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src_reg src0 = src_reg(v, glsl_type::float_type);
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src_reg src1 = src_reg(v, glsl_type::float_type);
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src_reg src2 = src_reg(v, glsl_type::float_type);
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src_reg zero(brw_imm_f(0.0f));
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bld.ADD(dest0, src0, src1);
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set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
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bld.CMP(bld.null_reg_f(), src_reg(dest0), zero, BRW_CONDITIONAL_GE);
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/* = Before =
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*
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* 0: add dest0 src0 src1
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* 1: (+f0) sel dest1 src2 0.0f
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* 2: cmp.ge.f0 null dest0 0.0f
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
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}
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TEST_F(cmod_propagation_vec4_test, intervening_dest_write)
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{
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const vec4_builder bld = vec4_builder(v).at_end();
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dst_reg dest = dst_reg(v, glsl_type::vec4_type);
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src_reg src0 = src_reg(v, glsl_type::float_type);
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src_reg src1 = src_reg(v, glsl_type::float_type);
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src_reg src2 = src_reg(v, glsl_type::vec2_type);
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src_reg zero(brw_imm_f(0.0f));
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bld.ADD(offset(dest, 8, 2), src0, src1);
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bld.emit(SHADER_OPCODE_TEX, dest, src2)
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->size_written = 4 * REG_SIZE;
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bld.CMP(bld.null_reg_f(), offset(src_reg(dest), 8, 2), zero, BRW_CONDITIONAL_GE);
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/* = Before =
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*
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* 0: add dest+2 src0 src1
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* 1: tex rlen 4 dest+0 src2
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* 2: cmp.ge.f0 null dest+2 0.0f
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
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EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
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}
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TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value)
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{
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const vec4_builder bld = vec4_builder(v).at_end();
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dst_reg dest0 = dst_reg(v, glsl_type::float_type);
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dst_reg dest1 = dst_reg(v, glsl_type::float_type);
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src_reg src0 = src_reg(v, glsl_type::float_type);
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src_reg src1 = src_reg(v, glsl_type::float_type);
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src_reg src2 = src_reg(v, glsl_type::float_type);
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src_reg zero(brw_imm_f(0.0f));
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dst_reg dest_null = bld.null_reg_f();
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dest_null.writemask = WRITEMASK_X;
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set_condmod(BRW_CONDITIONAL_GE, bld.ADD(dest0, src0, src1));
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set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
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bld.CMP(dest_null, src_reg(dest0), zero, BRW_CONDITIONAL_GE);
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/* = Before =
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*
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* 0: add.ge.f0 dest0 src0 src1
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* 1: (+f0) sel dest1 src2 0.0f
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* 2: cmp.ge.f0 null.x dest0 0.0f
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*
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* = After =
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* 0: add.ge.f0 dest0 src0 src1
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* 1: (+f0) sel dest1 src2 0.0f
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_TRUE(cmod_propagation(v));
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(1, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
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EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, negate)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
|
src_reg src0 = src_reg(v, glsl_type::float_type);
|
|
src_reg src1 = src_reg(v, glsl_type::float_type);
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
bld.ADD(dest, src0, src1);
|
|
src_reg tmp_src = src_reg(dest);
|
|
tmp_src.negate = true;
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
dest_null.writemask = WRITEMASK_X;
|
|
bld.CMP(dest_null, tmp_src, zero, BRW_CONDITIONAL_GE);
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: add dest src0 src1
|
|
* 1: cmp.ge.f0 null.x -dest 0.0f
|
|
*
|
|
* = After =
|
|
* 0: add.le.f0 dest src0 src1
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_TRUE(cmod_propagation(v));
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(0, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, movnz)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
|
src_reg src0 = src_reg(v, glsl_type::float_type);
|
|
src_reg src1 = src_reg(v, glsl_type::float_type);
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
dest_null.writemask = WRITEMASK_X;
|
|
|
|
bld.CMP(dest, src0, src1, BRW_CONDITIONAL_L);
|
|
set_condmod(BRW_CONDITIONAL_NZ,
|
|
bld.MOV(dest_null, src_reg(dest)));
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: cmp.l.f0 dest:F src0:F src1:F
|
|
* 1: mov.nz.f0 null.x dest:F
|
|
*
|
|
* = After =
|
|
* 0: cmp.l.f0 dest src0:F src1:F
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_TRUE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(0, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::int_type);
|
|
src_reg src0 = src_reg(v, glsl_type::int_type);
|
|
src_reg src1 = src_reg(v, glsl_type::int_type);
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
bld.ADD(dest, src0, src1);
|
|
bld.CMP(bld.null_reg_f(), retype(src_reg(dest), BRW_REGISTER_TYPE_F), zero,
|
|
BRW_CONDITIONAL_GE);
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: add dest:D src0:D src1:D
|
|
* 1: cmp.ge.f0 null:F dest:F 0.0f
|
|
*
|
|
* = After =
|
|
* (no changes)
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_FALSE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(1, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, andnz_non_one)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::int_type);
|
|
src_reg src0 = src_reg(v, glsl_type::float_type);
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
src_reg nonone(brw_imm_d(38));
|
|
|
|
bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L);
|
|
set_condmod(BRW_CONDITIONAL_NZ,
|
|
bld.AND(bld.null_reg_d(), src_reg(dest), nonone));
|
|
|
|
/* = Before =
|
|
* 0: cmp.l.f0 dest:F src0:F 0F
|
|
* 1: and.nz.f0 null:D dest:D 38D
|
|
*
|
|
* = After =
|
|
* (no changes)
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_FALSE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(1, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
|
|
EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
|
|
}
|
|
|
|
/* Note that basic is using glsl_type:float types, while this one is using
|
|
* glsl_type::vec4 */
|
|
TEST_F(cmod_propagation_vec4_test, basic_vec4)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
|
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
|
|
bld.MUL(dest, src0, src1);
|
|
bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_NZ);
|
|
|
|
/* = Before =
|
|
* 0: mul dest.xyzw src0.xyzw src1.xyzw
|
|
* 1: cmp.nz.f0.0 null.xyzw dest.xyzw 0.0f
|
|
*
|
|
* = After =
|
|
* 0: mul.nz.f0.0 dest.xyzw src0.xyzw src1.xyzw
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_TRUE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(0, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
|
dest.writemask = WRITEMASK_X;
|
|
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
|
|
bld.MUL(dest, src0, src1);
|
|
bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_NZ);
|
|
|
|
/* = Before =
|
|
* 0: mul dest.x src0 src1
|
|
* 1: cmp.nz.f0.0 null dest 0.0f
|
|
*
|
|
* = After =
|
|
* (no changes)
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_FALSE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(1, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
|
dest.writemask = WRITEMASK_X;
|
|
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg src2 = src_reg(v, glsl_type::vec4_type);
|
|
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
|
|
src2.negate = true;
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
src_reg tmp(dest);
|
|
tmp.swizzle = BRW_SWIZZLE_XXXX;
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
dest_null.writemask = WRITEMASK_X;
|
|
|
|
bld.MAD(dest, src0, src1, src2);
|
|
bld.CMP(dest_null, tmp, zero, BRW_CONDITIONAL_L);
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: mad dest.x:F src0.xxxx:F src10.xxxx:F -src2.xxxx:F
|
|
* 1: cmp.l.f0.0 null.x:F dest.xxxx:F 0.0f
|
|
*
|
|
* = After =
|
|
* 0: mad.l.f0 dest.x:F src0.xxxx:F src10.xxxx:F -src2.xxxx:F
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_TRUE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(0, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
|
dest.writemask = WRITEMASK_XW;
|
|
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg src2 = src_reg(v, glsl_type::vec4_type);
|
|
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
|
|
src2.negate = true;
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
src_reg tmp(dest);
|
|
tmp.swizzle = BRW_SWIZZLE_XXXX;
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
|
|
bld.MAD(dest, src0, src1, src2);
|
|
bld.CMP(dest_null, tmp, zero, BRW_CONDITIONAL_L);
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: mad dest.xw:F src0.xxxx:F src10.xxxx:F -src2.xxxx:F
|
|
* 1: cmp.l.f0.0 null:F dest.xxxx:F zeroF
|
|
*
|
|
* = After =
|
|
* (No changes)
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_FALSE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(1, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::ivec4_type);
|
|
dest.writemask = WRITEMASK_X;
|
|
src_reg src0 = src_reg(v, glsl_type::ivec4_type);
|
|
src0.swizzle = BRW_SWIZZLE_XXXX;
|
|
src0.file = UNIFORM;
|
|
src_reg nonone = retype(brw_imm_d(16), BRW_REGISTER_TYPE_D);
|
|
src_reg mov_src = src_reg(dest);
|
|
mov_src.swizzle = BRW_SWIZZLE_XXXX;
|
|
dst_reg dest_null = bld.null_reg_d();
|
|
dest_null.writemask = WRITEMASK_X;
|
|
|
|
bld.CMP(dest, src0, nonone, BRW_CONDITIONAL_GE);
|
|
set_condmod(BRW_CONDITIONAL_NZ,
|
|
bld.MOV(dest_null, mov_src));
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: cmp.ge.f0 dest.x:D u.xxxx:D 16D
|
|
* 1: mov.nz.f0 null.x:D dest.xxxx:D
|
|
*
|
|
* = After =
|
|
* 0: cmp.ge.f0 dest.x:D u.xxxx:D 16D
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_TRUE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(0, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
|
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
src_reg cmp_src = src_reg(dest);
|
|
cmp_src.swizzle = BRW_SWIZZLE4(0,1,3,2);
|
|
|
|
bld.MUL(dest, src0, src1);
|
|
bld.CMP(bld.null_reg_f(), cmp_src, zero, BRW_CONDITIONAL_NZ);
|
|
|
|
/* = Before =
|
|
* 0: mul dest src0 src1
|
|
* 1: cmp.nz.f0.0 null dest.xywz 0.0f
|
|
*
|
|
* = After =
|
|
* (No changes)
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_FALSE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(1, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
|
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
|
|
bld.ADD(dest, src0, src1);
|
|
vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE);
|
|
inst->src[1].negate = true;
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: add dest.xyzw src0 src1
|
|
* 1: cmp.ge.f0 null.xyzw src0 -src1
|
|
*
|
|
* = After =
|
|
* 0: add.ge.f0 dest.xyzw src0 src1
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_TRUE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(0, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
|
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
|
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
|
|
bld.ADD(dest, src0, src1);
|
|
vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE);
|
|
inst->src[1].negate = true;
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: add dest.x src0 src1
|
|
* 1: cmp.ge.f0 null.xyzw src0 -src1
|
|
*
|
|
* = After =
|
|
* (no changes)
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_FALSE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(1, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7)
|
|
{
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest1 = dst_reg(v, glsl_type::float_type);
|
|
dst_reg dest2 = dst_reg(v, glsl_type::float_type);
|
|
src_reg src0 = src_reg(v, glsl_type::float_type);
|
|
src_reg src1 = src_reg(v, glsl_type::float_type);
|
|
src_reg src2 = src_reg(v, glsl_type::float_type);
|
|
src_reg src3 = src_reg(v, glsl_type::float_type);
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
dest_null.writemask = WRITEMASK_X;
|
|
|
|
bld.ADD(dest1, src0, src1);
|
|
bld.SEL(dest2, src2, src3)
|
|
->conditional_mod = BRW_CONDITIONAL_GE;
|
|
bld.CMP(dest_null, src_reg(dest1), zero, BRW_CONDITIONAL_GE);
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: add dest1.x src0.xxxx src1.xxxx
|
|
* 1: sel.ge.f0 dest2.x src2.xxxx src3.xxxx
|
|
* 2: cmp.ge.f0 null.x dest.xxxx 0.0f
|
|
*
|
|
* = After =
|
|
* 0: add.ge.f0 dest.x src0.xxxx src1.xxxx
|
|
* 1: sel.ge.f0 dest2.x src2.xxxx src3.xxxx
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(2, block0->end_ip);
|
|
|
|
EXPECT_TRUE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(1, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
|
|
EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5)
|
|
{
|
|
devinfo->ver = 5;
|
|
devinfo->verx10 = devinfo->ver * 10;
|
|
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest1 = dst_reg(v, glsl_type::float_type);
|
|
dst_reg dest2 = dst_reg(v, glsl_type::float_type);
|
|
src_reg src0 = src_reg(v, glsl_type::float_type);
|
|
src_reg src1 = src_reg(v, glsl_type::float_type);
|
|
src_reg src2 = src_reg(v, glsl_type::float_type);
|
|
src_reg src3 = src_reg(v, glsl_type::float_type);
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
dest_null.writemask = WRITEMASK_X;
|
|
|
|
bld.ADD(dest1, src0, src1);
|
|
bld.SEL(dest2, src2, src3)
|
|
->conditional_mod = BRW_CONDITIONAL_GE;
|
|
bld.CMP(dest_null, src_reg(dest1), zero, BRW_CONDITIONAL_GE);
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: add dest1.x src0.xxxx src1.xxxx
|
|
* 1: sel.ge.f0 dest2.x src2.xxxx src3.xxxx
|
|
* 2: cmp.ge.f0 null.x dest.xxxx 0.0f
|
|
*
|
|
* = After =
|
|
* (no changes)
|
|
*
|
|
* On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented
|
|
* using a separate cmpn and sel instruction. This lowering occurs in
|
|
* fs_vistor::lower_minmax which is called a long time after the first
|
|
* calls to cmod_propagation.
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(2, block0->end_ip);
|
|
|
|
EXPECT_FALSE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(2, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
|
|
EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
|
|
}
|
|
|
|
TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5)
|
|
{
|
|
devinfo->ver = 5;
|
|
devinfo->verx10 = devinfo->ver * 10;
|
|
|
|
const vec4_builder bld = vec4_builder(v).at_end();
|
|
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
|
src_reg src0 = src_reg(v, glsl_type::float_type);
|
|
src_reg src1 = src_reg(v, glsl_type::float_type);
|
|
src_reg zero(brw_imm_f(0.0f));
|
|
dst_reg dest_null = bld.null_reg_f();
|
|
dest_null.writemask = WRITEMASK_X;
|
|
|
|
bld.SEL(dest, src0, src1)
|
|
->conditional_mod = BRW_CONDITIONAL_GE;
|
|
bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE);
|
|
|
|
/* = Before =
|
|
*
|
|
* 0: sel.ge.f0 dest.x src2.xxxx src3.xxxx
|
|
* 1: cmp.ge.f0 null.x dest.xxxx 0.0f
|
|
*
|
|
* = After =
|
|
* (no changes)
|
|
*
|
|
* Do not copy propagate into a sel.cond instruction. While it does modify
|
|
* the flags, the flags are not based on the result compared with zero (as
|
|
* with most other instructions). The result is based on the sources
|
|
* compared with each other (like cmp.cond).
|
|
*/
|
|
|
|
v->calculate_cfg();
|
|
bblock_t *block0 = v->cfg->blocks[0];
|
|
|
|
EXPECT_EQ(0, block0->start_ip);
|
|
EXPECT_EQ(1, block0->end_ip);
|
|
|
|
EXPECT_FALSE(cmod_propagation(v));
|
|
|
|
ASSERT_EQ(0, block0->start_ip);
|
|
ASSERT_EQ(1, block0->end_ip);
|
|
EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 0)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
|
|
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
|
|
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
|
|
}
|