225 lines
7.6 KiB
C++
225 lines
7.6 KiB
C++
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* \file brw_vec4_tes.cpp
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*
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* Tessellaton evaluation shader specific code derived from the vec4_visitor class.
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*/
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#include "brw_vec4_tes.h"
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#include "brw_cfg.h"
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#include "dev/intel_debug.h"
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namespace brw {
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vec4_tes_visitor::vec4_tes_visitor(const struct brw_compiler *compiler,
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void *log_data,
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const struct brw_tes_prog_key *key,
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struct brw_tes_prog_data *prog_data,
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const nir_shader *shader,
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void *mem_ctx,
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bool debug_enabled)
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: vec4_visitor(compiler, log_data, &key->base.tex, &prog_data->base,
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shader, mem_ctx, false, debug_enabled)
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{
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}
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void
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vec4_tes_visitor::setup_payload()
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{
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int reg = 0;
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/* The payload always contains important data in r0 and r1, which contains
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* the URB handles that are passed on to the URB write at the end
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* of the thread.
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*/
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reg += 2;
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reg = setup_uniforms(reg);
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foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
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for (int i = 0; i < 3; i++) {
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if (inst->src[i].file != ATTR)
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continue;
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unsigned slot = inst->src[i].nr + inst->src[i].offset / 16;
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struct brw_reg grf = brw_vec4_grf(reg + slot / 2, 4 * (slot % 2));
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grf = stride(grf, 0, 4, 1);
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grf.swizzle = inst->src[i].swizzle;
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grf.type = inst->src[i].type;
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grf.abs = inst->src[i].abs;
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grf.negate = inst->src[i].negate;
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inst->src[i] = grf;
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}
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}
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reg += 8 * prog_data->urb_read_length;
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this->first_non_payload_grf = reg;
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}
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void
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vec4_tes_visitor::emit_prolog()
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{
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input_read_header = src_reg(this, glsl_type::uvec4_type);
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emit(TES_OPCODE_CREATE_INPUT_READ_HEADER, dst_reg(input_read_header));
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this->current_annotation = NULL;
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}
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void
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vec4_tes_visitor::emit_urb_write_header(int mrf)
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{
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/* No need to do anything for DS; an implied write to this MRF will be
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* performed by VEC4_VS_OPCODE_URB_WRITE.
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*/
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(void) mrf;
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}
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vec4_instruction *
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vec4_tes_visitor::emit_urb_write_opcode(bool complete)
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{
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vec4_instruction *inst = emit(VEC4_VS_OPCODE_URB_WRITE);
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inst->urb_write_flags = complete ?
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BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS;
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return inst;
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}
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void
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vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
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{
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const struct brw_tes_prog_data *tes_prog_data =
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(const struct brw_tes_prog_data *) prog_data;
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switch (instr->intrinsic) {
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case nir_intrinsic_load_tess_coord:
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/* gl_TessCoord is part of the payload in g1 channels 0-2 and 4-6. */
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emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
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src_reg(brw_vec8_grf(1, 0))));
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break;
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case nir_intrinsic_load_tess_level_outer:
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if (tes_prog_data->domain == BRW_TESS_DOMAIN_ISOLINE) {
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emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
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swizzle(src_reg(ATTR, 1, glsl_type::vec4_type),
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BRW_SWIZZLE_ZWZW)));
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} else {
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emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
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swizzle(src_reg(ATTR, 1, glsl_type::vec4_type),
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BRW_SWIZZLE_WZYX)));
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}
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break;
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case nir_intrinsic_load_tess_level_inner:
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if (tes_prog_data->domain == BRW_TESS_DOMAIN_QUAD) {
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emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
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swizzle(src_reg(ATTR, 0, glsl_type::vec4_type),
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BRW_SWIZZLE_WZYX)));
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} else {
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emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
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src_reg(ATTR, 1, glsl_type::float_type)));
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}
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break;
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case nir_intrinsic_load_primitive_id:
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emit(TES_OPCODE_GET_PRIMITIVE_ID,
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get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
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break;
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case nir_intrinsic_load_input:
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case nir_intrinsic_load_per_vertex_input: {
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assert(nir_dest_bit_size(instr->dest) == 32);
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src_reg indirect_offset = get_indirect_offset(instr);
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unsigned imm_offset = instr->const_index[0];
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src_reg header = input_read_header;
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unsigned first_component = nir_intrinsic_component(instr);
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if (indirect_offset.file != BAD_FILE) {
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src_reg clamped_indirect_offset = src_reg(this, glsl_type::uvec4_type);
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/* Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the
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* valid range of the offset is [0, 0FFFFFFFh].
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*/
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emit_minmax(BRW_CONDITIONAL_L,
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dst_reg(clamped_indirect_offset),
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retype(indirect_offset, BRW_REGISTER_TYPE_UD),
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brw_imm_ud(0x0fffffffu));
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header = src_reg(this, glsl_type::uvec4_type);
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emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header),
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input_read_header, clamped_indirect_offset);
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} else {
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/* Arbitrarily only push up to 24 vec4 slots worth of data,
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* which is 12 registers (since each holds 2 vec4 slots).
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*/
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const unsigned max_push_slots = 24;
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if (imm_offset < max_push_slots) {
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src_reg src = src_reg(ATTR, imm_offset, glsl_type::ivec4_type);
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src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
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emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D), src));
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prog_data->urb_read_length =
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MAX2(prog_data->urb_read_length,
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DIV_ROUND_UP(imm_offset + 1, 2));
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break;
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}
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}
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dst_reg temp(this, glsl_type::ivec4_type);
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vec4_instruction *read =
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emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
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read->offset = imm_offset;
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read->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
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src_reg src = src_reg(temp);
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src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
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/* Copy to target. We might end up with some funky writemasks landing
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* in here, but we really don't want them in the above pseudo-ops.
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*/
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dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
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dst.writemask = brw_writemask_for_size(instr->num_components);
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emit(MOV(dst, src));
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break;
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}
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default:
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vec4_visitor::nir_emit_intrinsic(instr);
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}
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}
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void
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vec4_tes_visitor::emit_thread_end()
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{
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/* For DS, we always end the thread by emitting a single vertex.
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* emit_urb_write_opcode() will take care of setting the eot flag on the
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* SEND instruction.
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*/
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emit_vertex();
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}
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} /* namespace brw */
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