502 lines
18 KiB
C++
502 lines
18 KiB
C++
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* \file brw_vec4_tcs.cpp
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*
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* Tessellaton control shader specific code derived from the vec4_visitor class.
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*/
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#include "brw_nir.h"
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#include "brw_vec4_tcs.h"
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#include "brw_fs.h"
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#include "dev/intel_debug.h"
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namespace brw {
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vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
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void *log_data,
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const struct brw_tcs_prog_key *key,
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struct brw_tcs_prog_data *prog_data,
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const nir_shader *nir,
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void *mem_ctx,
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bool debug_enabled)
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: vec4_visitor(compiler, log_data, &key->base.tex, &prog_data->base,
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nir, mem_ctx, false, debug_enabled),
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key(key)
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{
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}
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void
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vec4_tcs_visitor::setup_payload()
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{
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int reg = 0;
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/* The payload always contains important data in r0, which contains
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* the URB handles that are passed on to the URB write at the end
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* of the thread.
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*/
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reg++;
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/* r1.0 - r4.7 may contain the input control point URB handles,
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* which we use to pull vertex data.
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*/
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reg += 4;
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/* Push constants may start at r5.0 */
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reg = setup_uniforms(reg);
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this->first_non_payload_grf = reg;
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}
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void
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vec4_tcs_visitor::emit_prolog()
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{
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invocation_id = src_reg(this, glsl_type::uint_type);
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emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
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/* HS threads are dispatched with the dispatch mask set to 0xFF.
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* If there are an odd number of output vertices, then the final
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* HS instance dispatched will only have its bottom half doing real
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* work, and so we need to disable the upper half:
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*/
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if (nir->info.tess.tcs_vertices_out % 2) {
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emit(CMP(dst_null_d(), invocation_id,
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brw_imm_ud(nir->info.tess.tcs_vertices_out),
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BRW_CONDITIONAL_L));
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/* Matching ENDIF is in emit_thread_end() */
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emit(IF(BRW_PREDICATE_NORMAL));
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}
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}
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void
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vec4_tcs_visitor::emit_thread_end()
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{
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vec4_instruction *inst;
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current_annotation = "thread end";
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if (nir->info.tess.tcs_vertices_out % 2) {
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emit(BRW_OPCODE_ENDIF);
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}
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if (devinfo->ver == 7) {
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struct brw_tcs_prog_data *tcs_prog_data =
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(struct brw_tcs_prog_data *) prog_data;
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current_annotation = "release input vertices";
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/* Synchronize all threads, so we know that no one is still
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* using the input URB handles.
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*/
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if (tcs_prog_data->instances > 1) {
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dst_reg header = dst_reg(this, glsl_type::uvec4_type);
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emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
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emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
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}
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/* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
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* We want to compare the bottom half of invocation_id with 0, but
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* use that truth value for the top half as well. Unfortunately,
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* we don't have stride in the vec4 world, nor UV immediates in
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* align16, so we need an opcode to get invocation_id<0,4,0>.
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*/
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set_condmod(BRW_CONDITIONAL_Z,
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emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
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invocation_id));
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emit(IF(BRW_PREDICATE_NORMAL));
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for (unsigned i = 0; i < key->input_vertices; i += 2) {
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/* If we have an odd number of input vertices, the last will be
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* unpaired. We don't want to use an interleaved URB write in
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* that case.
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*/
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const bool is_unpaired = i == key->input_vertices - 1;
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dst_reg header(this, glsl_type::uvec4_type);
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emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
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brw_imm_ud(is_unpaired));
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}
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emit(BRW_OPCODE_ENDIF);
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}
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inst = emit(TCS_OPCODE_THREAD_END);
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inst->base_mrf = 14;
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inst->mlen = 2;
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}
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void
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vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
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const src_reg &vertex_index,
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unsigned base_offset,
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unsigned first_component,
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const src_reg &indirect_offset)
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{
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vec4_instruction *inst;
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dst_reg temp(this, glsl_type::ivec4_type);
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temp.type = dst.type;
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/* Set up the message header to reference the proper parts of the URB */
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dst_reg header = dst_reg(this, glsl_type::uvec4_type);
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inst = emit(VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
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indirect_offset);
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inst->force_writemask_all = true;
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/* Read into a temporary, ignoring writemasking. */
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inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
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inst->offset = base_offset;
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inst->mlen = 1;
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inst->base_mrf = -1;
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/* Copy the temporary to the destination to deal with writemasking.
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*
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* Also attempt to deal with gl_PointSize being in the .w component.
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*/
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if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
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emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
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} else {
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src_reg src = src_reg(temp);
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src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
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emit(MOV(dst, src));
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}
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}
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void
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vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
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unsigned base_offset,
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unsigned first_component,
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const src_reg &indirect_offset)
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{
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vec4_instruction *inst;
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/* Set up the message header to reference the proper parts of the URB */
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dst_reg header = dst_reg(this, glsl_type::uvec4_type);
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inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
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brw_imm_ud(dst.writemask << first_component), indirect_offset);
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inst->force_writemask_all = true;
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vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
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read->offset = base_offset;
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read->mlen = 1;
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read->base_mrf = -1;
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if (first_component) {
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/* Read into a temporary and copy with a swizzle and writemask. */
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read->dst = retype(dst_reg(this, glsl_type::ivec4_type), dst.type);
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emit(MOV(dst, swizzle(src_reg(read->dst),
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BRW_SWZ_COMP_INPUT(first_component))));
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}
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}
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void
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vec4_tcs_visitor::emit_urb_write(const src_reg &value,
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unsigned writemask,
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unsigned base_offset,
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const src_reg &indirect_offset)
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{
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if (writemask == 0)
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return;
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src_reg message(this, glsl_type::uvec4_type, 2);
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vec4_instruction *inst;
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inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
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brw_imm_ud(writemask), indirect_offset);
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inst->force_writemask_all = true;
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inst = emit(MOV(byte_offset(dst_reg(retype(message, value.type)), REG_SIZE),
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value));
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inst->force_writemask_all = true;
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inst = emit(VEC4_TCS_OPCODE_URB_WRITE, dst_null_f(), message);
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inst->offset = base_offset;
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inst->mlen = 2;
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inst->base_mrf = -1;
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}
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void
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vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
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{
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switch (instr->intrinsic) {
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case nir_intrinsic_load_invocation_id:
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emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
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invocation_id));
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break;
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case nir_intrinsic_load_primitive_id:
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emit(TCS_OPCODE_GET_PRIMITIVE_ID,
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get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
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break;
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case nir_intrinsic_load_patch_vertices_in:
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emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
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brw_imm_d(key->input_vertices)));
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break;
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case nir_intrinsic_load_per_vertex_input: {
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assert(nir_dest_bit_size(instr->dest) == 32);
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src_reg indirect_offset = get_indirect_offset(instr);
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unsigned imm_offset = instr->const_index[0];
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src_reg vertex_index = retype(get_nir_src_imm(instr->src[0]),
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BRW_REGISTER_TYPE_UD);
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unsigned first_component = nir_intrinsic_component(instr);
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dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
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dst.writemask = brw_writemask_for_size(instr->num_components);
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emit_input_urb_read(dst, vertex_index, imm_offset,
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first_component, indirect_offset);
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break;
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}
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case nir_intrinsic_load_input:
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unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
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break;
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case nir_intrinsic_load_output:
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case nir_intrinsic_load_per_vertex_output: {
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src_reg indirect_offset = get_indirect_offset(instr);
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unsigned imm_offset = instr->const_index[0];
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dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
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dst.writemask = brw_writemask_for_size(instr->num_components);
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emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr),
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indirect_offset);
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break;
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}
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case nir_intrinsic_store_output:
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case nir_intrinsic_store_per_vertex_output: {
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assert(nir_src_bit_size(instr->src[0]) == 32);
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src_reg value = get_nir_src(instr->src[0]);
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unsigned mask = instr->const_index[1];
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unsigned swiz = BRW_SWIZZLE_XYZW;
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src_reg indirect_offset = get_indirect_offset(instr);
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unsigned imm_offset = instr->const_index[0];
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unsigned first_component = nir_intrinsic_component(instr);
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if (first_component) {
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assert(swiz == BRW_SWIZZLE_XYZW);
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swiz = BRW_SWZ_COMP_OUTPUT(first_component);
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mask = mask << first_component;
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}
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emit_urb_write(swizzle(value, swiz), mask,
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imm_offset, indirect_offset);
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break;
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}
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case nir_intrinsic_control_barrier: {
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dst_reg header = dst_reg(this, glsl_type::uvec4_type);
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emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
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emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
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break;
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}
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case nir_intrinsic_memory_barrier_tcs_patch:
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break;
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default:
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vec4_visitor::nir_emit_intrinsic(instr);
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}
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}
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/**
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* Return the number of patches to accumulate before an 8_PATCH mode thread is
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* launched. In cases with a large number of input control points and a large
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* amount of VS outputs, the VS URB space needed to store an entire 8 patches
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* worth of data can be prohibitive, so it can be beneficial to launch threads
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* early.
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*
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* See the 3DSTATE_HS::Patch Count Threshold documentation for the recommended
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* values. Note that 0 means to "disable" early dispatch, meaning to wait for
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* a full 8 patches as normal.
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*/
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static int
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get_patch_count_threshold(int input_control_points)
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{
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if (input_control_points <= 4)
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return 0;
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else if (input_control_points <= 6)
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return 5;
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else if (input_control_points <= 8)
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return 4;
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else if (input_control_points <= 10)
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return 3;
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else if (input_control_points <= 14)
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return 2;
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/* Return patch count 1 for PATCHLIST_15 - PATCHLIST_32 */
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return 1;
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}
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} /* namespace brw */
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extern "C" const unsigned *
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brw_compile_tcs(const struct brw_compiler *compiler,
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void *mem_ctx,
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struct brw_compile_tcs_params *params)
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{
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const struct intel_device_info *devinfo = compiler->devinfo;
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nir_shader *nir = params->nir;
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const struct brw_tcs_prog_key *key = params->key;
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struct brw_tcs_prog_data *prog_data = params->prog_data;
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struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
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const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
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const bool debug_enabled = INTEL_DEBUG(DEBUG_TCS);
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const unsigned *assembly;
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vue_prog_data->base.stage = MESA_SHADER_TESS_CTRL;
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prog_data->base.base.ray_queries = nir->info.ray_queries;
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prog_data->base.base.total_scratch = 0;
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nir->info.outputs_written = key->outputs_written;
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nir->info.patch_outputs_written = key->patch_outputs_written;
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struct brw_vue_map input_vue_map;
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brw_compute_vue_map(devinfo, &input_vue_map, nir->info.inputs_read,
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nir->info.separate_shader, 1);
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brw_compute_tess_vue_map(&vue_prog_data->vue_map,
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nir->info.outputs_written,
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nir->info.patch_outputs_written);
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brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
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brw_nir_lower_vue_inputs(nir, &input_vue_map);
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brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
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key->_tes_primitive_mode);
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if (key->quads_workaround)
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brw_nir_apply_tcs_quads_workaround(nir);
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brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled,
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key->base.robust_buffer_access);
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bool has_primitive_id =
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BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
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prog_data->patch_count_threshold = brw::get_patch_count_threshold(key->input_vertices);
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if (compiler->use_tcs_8_patch &&
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nir->info.tess.tcs_vertices_out <= (devinfo->ver >= 12 ? 32 : 16) &&
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2 + has_primitive_id + key->input_vertices <= (devinfo->ver >= 12 ? 63 : 31)) {
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/* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the
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* "Instance" field limits the number of output vertices to [1, 16] on
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* gfx11 and below, or [1, 32] on gfx12 and above. Secondly, the
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* "Dispatch GRF Start Register for URB Data" field is limited to [0,
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* 31] - which imposes a limit on the input vertices.
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*/
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vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH;
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prog_data->instances = nir->info.tess.tcs_vertices_out;
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prog_data->include_primitive_id = has_primitive_id;
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} else {
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unsigned verts_per_thread = is_scalar ? 8 : 2;
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vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_SINGLE_PATCH;
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prog_data->instances =
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DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, verts_per_thread);
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}
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/* Compute URB entry size. The maximum allowed URB entry size is 32k.
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* That divides up as follows:
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*
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* 32 bytes for the patch header (tessellation factors)
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* 480 bytes for per-patch varyings (a varying component is 4 bytes and
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* gl_MaxTessPatchComponents = 120)
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* 16384 bytes for per-vertex varyings (a varying component is 4 bytes,
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* gl_MaxPatchVertices = 32 and
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* gl_MaxTessControlOutputComponents = 128)
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*
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* 15808 bytes left for varying packing overhead
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*/
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const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
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const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
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unsigned output_size_bytes = 0;
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/* Note that the patch header is counted in num_per_patch_slots. */
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output_size_bytes += num_per_patch_slots * 16;
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output_size_bytes += nir->info.tess.tcs_vertices_out *
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num_per_vertex_slots * 16;
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assert(output_size_bytes >= 1);
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if (output_size_bytes > GFX7_MAX_HS_URB_ENTRY_SIZE_BYTES)
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return NULL;
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/* URB entry sizes are stored as a multiple of 64 bytes. */
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vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
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/* HS does not use the usual payload pushing from URB to GRFs,
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* because we don't have enough registers for a full-size payload, and
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* the hardware is broken on Haswell anyway.
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*/
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vue_prog_data->urb_read_length = 0;
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if (unlikely(debug_enabled)) {
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fprintf(stderr, "TCS Input ");
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brw_print_vue_map(stderr, &input_vue_map, MESA_SHADER_TESS_CTRL);
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fprintf(stderr, "TCS Output ");
|
|
brw_print_vue_map(stderr, &vue_prog_data->vue_map, MESA_SHADER_TESS_CTRL);
|
|
}
|
|
|
|
if (is_scalar) {
|
|
fs_visitor v(compiler, params->log_data, mem_ctx, &key->base,
|
|
&prog_data->base.base, nir, 8, debug_enabled);
|
|
if (!v.run_tcs()) {
|
|
params->error_str = ralloc_strdup(mem_ctx, v.fail_msg);
|
|
return NULL;
|
|
}
|
|
|
|
prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
|
|
|
|
fs_generator g(compiler, params->log_data, mem_ctx,
|
|
&prog_data->base.base, false, MESA_SHADER_TESS_CTRL);
|
|
if (unlikely(debug_enabled)) {
|
|
g.enable_debug(ralloc_asprintf(mem_ctx,
|
|
"%s tessellation control shader %s",
|
|
nir->info.label ? nir->info.label
|
|
: "unnamed",
|
|
nir->info.name));
|
|
}
|
|
|
|
g.generate_code(v.cfg, 8, v.shader_stats,
|
|
v.performance_analysis.require(), params->stats);
|
|
|
|
g.add_const_data(nir->constant_data, nir->constant_data_size);
|
|
|
|
assembly = g.get_assembly();
|
|
} else {
|
|
brw::vec4_tcs_visitor v(compiler, params->log_data, key, prog_data,
|
|
nir, mem_ctx, debug_enabled);
|
|
if (!v.run()) {
|
|
params->error_str = ralloc_strdup(mem_ctx, v.fail_msg);
|
|
return NULL;
|
|
}
|
|
|
|
if (INTEL_DEBUG(DEBUG_TCS))
|
|
v.dump_instructions();
|
|
|
|
|
|
assembly = brw_vec4_generate_assembly(compiler, params->log_data, mem_ctx, nir,
|
|
&prog_data->base, v.cfg,
|
|
v.performance_analysis.require(),
|
|
params->stats, debug_enabled);
|
|
}
|
|
|
|
return assembly;
|
|
}
|