214 lines
8.2 KiB
C++
214 lines
8.2 KiB
C++
/*
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* Copyright © 2013-2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_vec4_surface_builder.h"
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using namespace brw;
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namespace {
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namespace array_utils {
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/**
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* Copy one every \p src_stride logical components of the argument into
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* one every \p dst_stride logical components of the result.
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*/
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static src_reg
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emit_stride(const vec4_builder &bld, const src_reg &src, unsigned size,
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unsigned dst_stride, unsigned src_stride)
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{
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if (src_stride == 1 && dst_stride == 1) {
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return src;
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} else {
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const dst_reg dst = bld.vgrf(src.type,
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DIV_ROUND_UP(size * dst_stride, 4));
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for (unsigned i = 0; i < size; ++i)
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bld.MOV(writemask(offset(dst, 8, i * dst_stride / 4),
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1 << (i * dst_stride % 4)),
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swizzle(offset(src, 8, i * src_stride / 4),
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brw_swizzle_for_mask(1 << (i * src_stride % 4))));
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return src_reg(dst);
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}
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}
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/**
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* Convert a VEC4 into an array of registers with the layout expected by
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* the recipient shared unit. If \p has_simd4x2 is true the argument is
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* left unmodified in SIMD4x2 form, otherwise it will be rearranged into
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* a SIMD8 vector.
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*/
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static src_reg
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emit_insert(const vec4_builder &bld, const src_reg &src,
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unsigned n, bool has_simd4x2)
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{
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if (src.file == BAD_FILE || n == 0) {
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return src_reg();
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} else {
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/* Pad unused components with zeroes. */
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const unsigned mask = (1 << n) - 1;
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const dst_reg tmp = bld.vgrf(src.type);
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bld.MOV(writemask(tmp, mask), src);
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if (n < 4)
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bld.MOV(writemask(tmp, ~mask), brw_imm_d(0));
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return emit_stride(bld, src_reg(tmp), n, has_simd4x2 ? 1 : 4, 1);
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}
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}
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}
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}
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namespace brw {
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namespace surface_access {
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namespace {
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using namespace array_utils;
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/**
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* Generate a send opcode for a surface message and return the
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* result.
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*/
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src_reg
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emit_send(const vec4_builder &bld, enum opcode op,
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const src_reg &header,
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const src_reg &addr, unsigned addr_sz,
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const src_reg &src, unsigned src_sz,
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const src_reg &surface,
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unsigned arg, unsigned ret_sz,
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brw_predicate pred = BRW_PREDICATE_NONE)
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{
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/* Calculate the total number of components of the payload. */
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const unsigned header_sz = (header.file == BAD_FILE ? 0 : 1);
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const unsigned sz = header_sz + addr_sz + src_sz;
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/* Construct the payload. */
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const dst_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, sz);
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unsigned n = 0;
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if (header_sz)
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bld.exec_all().MOV(offset(payload, 8, n++),
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retype(header, BRW_REGISTER_TYPE_UD));
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for (unsigned i = 0; i < addr_sz; i++)
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bld.MOV(offset(payload, 8, n++),
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offset(retype(addr, BRW_REGISTER_TYPE_UD), 8, i));
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for (unsigned i = 0; i < src_sz; i++)
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bld.MOV(offset(payload, 8, n++),
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offset(retype(src, BRW_REGISTER_TYPE_UD), 8, i));
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/* Reduce the dynamically uniform surface index to a single
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* scalar.
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*/
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const src_reg usurface = bld.emit_uniformize(surface);
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/* Emit the message send instruction. */
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const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, ret_sz);
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vec4_instruction *inst =
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bld.emit(op, dst, src_reg(payload), usurface, brw_imm_ud(arg));
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inst->mlen = sz;
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inst->size_written = ret_sz * REG_SIZE;
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inst->header_size = header_sz;
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inst->predicate = pred;
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return src_reg(dst);
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}
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}
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/**
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* Emit an untyped surface read opcode. \p dims determines the number
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* of components of the address and \p size the number of components of
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* the returned value.
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*/
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src_reg
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emit_untyped_read(const vec4_builder &bld,
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const src_reg &surface, const src_reg &addr,
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unsigned dims, unsigned size,
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brw_predicate pred)
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{
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return emit_send(bld, VEC4_OPCODE_UNTYPED_SURFACE_READ, src_reg(),
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emit_insert(bld, addr, dims, true), 1,
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src_reg(), 0,
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surface, size, 1, pred);
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}
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/**
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* Emit an untyped surface write opcode. \p dims determines the number
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* of components of the address and \p size the number of components of
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* the argument.
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*/
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void
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emit_untyped_write(const vec4_builder &bld, const src_reg &surface,
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const src_reg &addr, const src_reg &src,
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unsigned dims, unsigned size,
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brw_predicate pred)
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{
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const bool has_simd4x2 = bld.shader->devinfo->verx10 == 75;
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emit_send(bld, VEC4_OPCODE_UNTYPED_SURFACE_WRITE, src_reg(),
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emit_insert(bld, addr, dims, has_simd4x2),
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has_simd4x2 ? 1 : dims,
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emit_insert(bld, src, size, has_simd4x2),
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has_simd4x2 ? 1 : size,
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surface, size, 0, pred);
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}
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/**
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* Emit an untyped surface atomic opcode. \p dims determines the number
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* of components of the address and \p rsize the number of components of
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* the returned value (either zero or one).
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*/
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src_reg
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emit_untyped_atomic(const vec4_builder &bld,
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const src_reg &surface, const src_reg &addr,
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const src_reg &src0, const src_reg &src1,
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unsigned dims, unsigned rsize, unsigned op,
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brw_predicate pred)
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{
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const bool has_simd4x2 = bld.shader->devinfo->verx10 == 75;
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/* Zip the components of both sources, they are represented as the X
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* and Y components of the same vector.
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*/
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const unsigned size = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
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const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD);
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if (size >= 1) {
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bld.MOV(writemask(srcs, WRITEMASK_X),
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swizzle(src0, BRW_SWIZZLE_XXXX));
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}
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if (size >= 2) {
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bld.MOV(writemask(srcs, WRITEMASK_Y),
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swizzle(src1, BRW_SWIZZLE_XXXX));
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}
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return emit_send(bld, VEC4_OPCODE_UNTYPED_ATOMIC, src_reg(),
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emit_insert(bld, addr, dims, has_simd4x2),
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has_simd4x2 ? 1 : dims,
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emit_insert(bld, src_reg(srcs), size, has_simd4x2),
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has_simd4x2 && size ? 1 : size,
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surface, op, rsize, pred);
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}
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}
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}
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