511 lines
18 KiB
C++
511 lines
18 KiB
C++
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "util/register_allocate.h"
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#include "brw_vec4.h"
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#include "brw_cfg.h"
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using namespace brw;
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namespace brw {
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static void
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assign(unsigned int *reg_hw_locations, backend_reg *reg)
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{
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if (reg->file == VGRF) {
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reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE;
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reg->offset %= REG_SIZE;
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}
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}
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bool
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vec4_visitor::reg_allocate_trivial()
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{
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unsigned int hw_reg_mapping[this->alloc.count];
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bool virtual_grf_used[this->alloc.count];
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int next;
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/* Calculate which virtual GRFs are actually in use after whatever
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* optimization passes have occurred.
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*/
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for (unsigned i = 0; i < this->alloc.count; i++) {
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virtual_grf_used[i] = false;
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}
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foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
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if (inst->dst.file == VGRF)
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virtual_grf_used[inst->dst.nr] = true;
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for (unsigned i = 0; i < 3; i++) {
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if (inst->src[i].file == VGRF)
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virtual_grf_used[inst->src[i].nr] = true;
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}
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}
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hw_reg_mapping[0] = this->first_non_payload_grf;
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next = hw_reg_mapping[0] + this->alloc.sizes[0];
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for (unsigned i = 1; i < this->alloc.count; i++) {
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if (virtual_grf_used[i]) {
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hw_reg_mapping[i] = next;
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next += this->alloc.sizes[i];
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}
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}
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prog_data->total_grf = next;
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foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
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assign(hw_reg_mapping, &inst->dst);
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assign(hw_reg_mapping, &inst->src[0]);
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assign(hw_reg_mapping, &inst->src[1]);
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assign(hw_reg_mapping, &inst->src[2]);
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}
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if (prog_data->total_grf > max_grf) {
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fail("Ran out of regs on trivial allocator (%d/%d)\n",
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prog_data->total_grf, max_grf);
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return false;
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}
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return true;
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}
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extern "C" void
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brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
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{
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int base_reg_count =
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compiler->devinfo->ver >= 7 ? GFX7_MRF_HACK_START : BRW_MAX_GRF;
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assert(compiler->devinfo->ver < 8);
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/* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
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* SEND-from-GRF sources cannot be split, so we also need classes for each
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* potential message length.
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*/
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const int class_count = MAX_VGRF_SIZE;
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int class_sizes[MAX_VGRF_SIZE];
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for (int i = 0; i < class_count; i++)
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class_sizes[i] = i + 1;
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ralloc_free(compiler->vec4_reg_set.regs);
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compiler->vec4_reg_set.regs = ra_alloc_reg_set(compiler, base_reg_count, false);
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if (compiler->devinfo->ver >= 6)
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ra_set_allocate_round_robin(compiler->vec4_reg_set.regs);
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ralloc_free(compiler->vec4_reg_set.classes);
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compiler->vec4_reg_set.classes = ralloc_array(compiler, struct ra_class *, class_count);
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/* Now, add the registers to their classes, and add the conflicts
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* between them and the base GRF registers (and also each other).
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*/
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for (int i = 0; i < class_count; i++) {
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int class_reg_count = base_reg_count - (class_sizes[i] - 1);
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compiler->vec4_reg_set.classes[i] =
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ra_alloc_contig_reg_class(compiler->vec4_reg_set.regs, class_sizes[i]);
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for (int j = 0; j < class_reg_count; j++)
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ra_class_add_reg(compiler->vec4_reg_set.classes[i], j);
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}
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ra_set_finalize(compiler->vec4_reg_set.regs, NULL);
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}
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void
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vec4_visitor::setup_payload_interference(struct ra_graph *g,
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int first_payload_node,
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int reg_node_count)
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{
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int payload_node_count = this->first_non_payload_grf;
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for (int i = 0; i < payload_node_count; i++) {
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/* Mark each payload reg node as being allocated to its physical register.
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*
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* The alternative would be to have per-physical register classes, which
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* would just be silly.
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*/
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ra_set_node_reg(g, first_payload_node + i, i);
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/* For now, just mark each payload node as interfering with every other
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* node to be allocated.
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*/
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for (int j = 0; j < reg_node_count; j++) {
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ra_add_node_interference(g, first_payload_node + i, j);
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}
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}
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}
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bool
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vec4_visitor::reg_allocate()
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{
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unsigned int hw_reg_mapping[alloc.count];
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int payload_reg_count = this->first_non_payload_grf;
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/* Using the trivial allocator can be useful in debugging undefined
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* register access as a result of broken optimization passes.
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*/
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if (0)
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return reg_allocate_trivial();
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assert(devinfo->ver < 8);
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const vec4_live_variables &live = live_analysis.require();
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int node_count = alloc.count;
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int first_payload_node = node_count;
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node_count += payload_reg_count;
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struct ra_graph *g =
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ra_alloc_interference_graph(compiler->vec4_reg_set.regs, node_count);
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for (unsigned i = 0; i < alloc.count; i++) {
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int size = this->alloc.sizes[i];
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assert(size >= 1 && size <= MAX_VGRF_SIZE);
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ra_set_node_class(g, i, compiler->vec4_reg_set.classes[size - 1]);
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for (unsigned j = 0; j < i; j++) {
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if (live.vgrfs_interfere(i, j)) {
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ra_add_node_interference(g, i, j);
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}
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}
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}
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/* Certain instructions can't safely use the same register for their
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* sources and destination. Add interference.
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*/
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foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
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if (inst->dst.file == VGRF && inst->has_source_and_destination_hazard()) {
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for (unsigned i = 0; i < 3; i++) {
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if (inst->src[i].file == VGRF) {
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ra_add_node_interference(g, inst->dst.nr, inst->src[i].nr);
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}
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}
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}
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}
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setup_payload_interference(g, first_payload_node, node_count);
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if (!ra_allocate(g)) {
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/* Failed to allocate registers. Spill a reg, and the caller will
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* loop back into here to try again.
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*/
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int reg = choose_spill_reg(g);
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if (this->no_spills) {
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fail("Failure to register allocate. Reduce number of live "
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"values to avoid this.");
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} else if (reg == -1) {
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fail("no register to spill\n");
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} else {
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spill_reg(reg);
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}
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ralloc_free(g);
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return false;
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}
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/* Get the chosen virtual registers for each node, and map virtual
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* regs in the register classes back down to real hardware reg
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* numbers.
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*/
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prog_data->total_grf = payload_reg_count;
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for (unsigned i = 0; i < alloc.count; i++) {
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hw_reg_mapping[i] = ra_get_node_reg(g, i);
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prog_data->total_grf = MAX2(prog_data->total_grf,
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hw_reg_mapping[i] + alloc.sizes[i]);
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}
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foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
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assign(hw_reg_mapping, &inst->dst);
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assign(hw_reg_mapping, &inst->src[0]);
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assign(hw_reg_mapping, &inst->src[1]);
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assign(hw_reg_mapping, &inst->src[2]);
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}
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ralloc_free(g);
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return true;
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}
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/**
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* When we decide to spill a register, instead of blindly spilling every use,
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* save unspills when the spill register is used (read) in consecutive
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* instructions. This can potentially save a bunch of unspills that would
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* have very little impact in register allocation anyway.
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*
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* Notice that we need to account for this behavior when spilling a register
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* and when evaluating spilling costs. This function is designed so it can
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* be called from both places and avoid repeating the logic.
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*
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* - When we call this function from spill_reg(), we pass in scratch_reg the
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* actual unspill/spill register that we want to reuse in the current
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* instruction.
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*
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* - When we call this from evaluate_spill_costs(), we pass the register for
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* which we are evaluating spilling costs.
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*
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* In either case, we check if the previous instructions read scratch_reg until
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* we find one that writes to it with a compatible mask or does not read/write
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* scratch_reg at all.
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*/
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static bool
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can_use_scratch_for_source(const vec4_instruction *inst, unsigned i,
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unsigned scratch_reg)
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{
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assert(inst->src[i].file == VGRF);
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bool prev_inst_read_scratch_reg = false;
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/* See if any previous source in the same instructions reads scratch_reg */
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for (unsigned n = 0; n < i; n++) {
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if (inst->src[n].file == VGRF && inst->src[n].nr == scratch_reg)
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prev_inst_read_scratch_reg = true;
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}
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/* Now check if previous instructions read/write scratch_reg */
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for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev;
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!prev_inst->is_head_sentinel();
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prev_inst = (vec4_instruction *) prev_inst->prev) {
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/* If the previous instruction writes to scratch_reg then we can reuse
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* it if the write is not conditional and the channels we write are
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* compatible with our read mask
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*/
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if (prev_inst->dst.file == VGRF && prev_inst->dst.nr == scratch_reg) {
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return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) &&
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(brw_mask_for_swizzle(inst->src[i].swizzle) &
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~prev_inst->dst.writemask) == 0;
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}
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/* Skip scratch read/writes so that instructions generated by spilling
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* other registers (that won't read/write scratch_reg) do not stop us from
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* reusing scratch_reg for this instruction.
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*/
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if (prev_inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE ||
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prev_inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_READ)
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continue;
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/* If the previous instruction does not write to scratch_reg, then check
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* if it reads it
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*/
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int n;
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for (n = 0; n < 3; n++) {
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if (prev_inst->src[n].file == VGRF &&
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prev_inst->src[n].nr == scratch_reg) {
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prev_inst_read_scratch_reg = true;
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break;
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}
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}
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if (n == 3) {
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/* The previous instruction does not read scratch_reg. At this point,
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* if no previous instruction has read scratch_reg it means that we
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* will need to unspill it here and we can't reuse it (so we return
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* false). Otherwise, if we found at least one consecutive instruction
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* that read scratch_reg, then we know that we got here from
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* evaluate_spill_costs (since for the spill_reg path any block of
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* consecutive instructions using scratch_reg must start with a write
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* to that register, so we would've exited the loop in the check for
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* the write that we have at the start of this loop), and in that case
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* it means that we found the point at which the scratch_reg would be
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* unspilled. Since we always unspill a full vec4, it means that we
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* have all the channels available and we can just return true to
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* signal that we can reuse the register in the current instruction
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* too.
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*/
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return prev_inst_read_scratch_reg;
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}
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}
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return prev_inst_read_scratch_reg;
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}
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static inline float
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spill_cost_for_type(enum brw_reg_type type)
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{
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/* Spilling of a 64-bit register involves emitting 2 32-bit scratch
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* messages plus the 64b/32b shuffling code.
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*/
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return type_sz(type) == 8 ? 2.25f : 1.0f;
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}
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void
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vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
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{
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float loop_scale = 1.0;
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unsigned *reg_type_size = (unsigned *)
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ralloc_size(NULL, this->alloc.count * sizeof(unsigned));
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for (unsigned i = 0; i < this->alloc.count; i++) {
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spill_costs[i] = 0.0;
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no_spill[i] = alloc.sizes[i] != 1 && alloc.sizes[i] != 2;
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reg_type_size[i] = 0;
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}
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/* Calculate costs for spilling nodes. Call it a cost of 1 per
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* spill/unspill we'll have to do, and guess that the insides of
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* loops run 10 times.
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*/
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foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
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for (unsigned int i = 0; i < 3; i++) {
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if (inst->src[i].file == VGRF && !no_spill[inst->src[i].nr]) {
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/* We will only unspill src[i] it it wasn't unspilled for the
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* previous instruction, in which case we'll just reuse the scratch
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* reg for this instruction.
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*/
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if (!can_use_scratch_for_source(inst, i, inst->src[i].nr)) {
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spill_costs[inst->src[i].nr] +=
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loop_scale * spill_cost_for_type(inst->src[i].type);
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if (inst->src[i].reladdr ||
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inst->src[i].offset >= REG_SIZE)
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no_spill[inst->src[i].nr] = true;
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/* We don't support unspills of partial DF reads.
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*
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* Our 64-bit unspills are implemented with two 32-bit scratch
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* messages, each one reading that for both SIMD4x2 threads that
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* we need to shuffle into correct 64-bit data. Ensure that we
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* are reading data for both threads.
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*/
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if (type_sz(inst->src[i].type) == 8 && inst->exec_size != 8)
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no_spill[inst->src[i].nr] = true;
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}
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/* We can't spill registers that mix 32-bit and 64-bit access (that
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* contain 64-bit data that is operated on via 32-bit instructions)
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*/
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unsigned type_size = type_sz(inst->src[i].type);
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if (reg_type_size[inst->src[i].nr] == 0)
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reg_type_size[inst->src[i].nr] = type_size;
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else if (reg_type_size[inst->src[i].nr] != type_size)
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no_spill[inst->src[i].nr] = true;
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}
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}
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if (inst->dst.file == VGRF && !no_spill[inst->dst.nr]) {
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spill_costs[inst->dst.nr] +=
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loop_scale * spill_cost_for_type(inst->dst.type);
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if (inst->dst.reladdr || inst->dst.offset >= REG_SIZE)
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no_spill[inst->dst.nr] = true;
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/* We don't support spills of partial DF writes.
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*
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* Our 64-bit spills are implemented with two 32-bit scratch messages,
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* each one writing that for both SIMD4x2 threads. Ensure that we
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* are writing data for both threads.
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*/
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if (type_sz(inst->dst.type) == 8 && inst->exec_size != 8)
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no_spill[inst->dst.nr] = true;
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/* We can't spill registers that mix 32-bit and 64-bit access (that
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* contain 64-bit data that is operated on via 32-bit instructions)
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*/
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unsigned type_size = type_sz(inst->dst.type);
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if (reg_type_size[inst->dst.nr] == 0)
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reg_type_size[inst->dst.nr] = type_size;
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else if (reg_type_size[inst->dst.nr] != type_size)
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no_spill[inst->dst.nr] = true;
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}
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switch (inst->opcode) {
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case BRW_OPCODE_DO:
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loop_scale *= 10;
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break;
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case BRW_OPCODE_WHILE:
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loop_scale /= 10;
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break;
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case SHADER_OPCODE_GFX4_SCRATCH_READ:
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case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
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case VEC4_OPCODE_MOV_FOR_SCRATCH:
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for (int i = 0; i < 3; i++) {
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if (inst->src[i].file == VGRF)
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no_spill[inst->src[i].nr] = true;
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}
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if (inst->dst.file == VGRF)
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no_spill[inst->dst.nr] = true;
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break;
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default:
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break;
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}
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}
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ralloc_free(reg_type_size);
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}
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int
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vec4_visitor::choose_spill_reg(struct ra_graph *g)
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{
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float spill_costs[this->alloc.count];
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bool no_spill[this->alloc.count];
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evaluate_spill_costs(spill_costs, no_spill);
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for (unsigned i = 0; i < this->alloc.count; i++) {
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if (!no_spill[i])
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ra_set_node_spill_cost(g, i, spill_costs[i]);
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}
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return ra_get_best_spill_node(g);
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}
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void
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vec4_visitor::spill_reg(unsigned spill_reg_nr)
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{
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assert(alloc.sizes[spill_reg_nr] == 1 || alloc.sizes[spill_reg_nr] == 2);
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unsigned spill_offset = last_scratch;
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|
last_scratch += alloc.sizes[spill_reg_nr];
|
|
|
|
/* Generate spill/unspill instructions for the objects being spilled. */
|
|
unsigned scratch_reg = ~0u;
|
|
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
|
|
for (unsigned i = 0; i < 3; i++) {
|
|
if (inst->src[i].file == VGRF && inst->src[i].nr == spill_reg_nr) {
|
|
if (scratch_reg == ~0u ||
|
|
!can_use_scratch_for_source(inst, i, scratch_reg)) {
|
|
/* We need to unspill anyway so make sure we read the full vec4
|
|
* in any case. This way, the cached register can be reused
|
|
* for consecutive instructions that read different channels of
|
|
* the same vec4.
|
|
*/
|
|
scratch_reg = alloc.allocate(alloc.sizes[spill_reg_nr]);
|
|
src_reg temp = inst->src[i];
|
|
temp.nr = scratch_reg;
|
|
temp.offset = 0;
|
|
temp.swizzle = BRW_SWIZZLE_XYZW;
|
|
emit_scratch_read(block, inst,
|
|
dst_reg(temp), inst->src[i], spill_offset);
|
|
temp.offset = inst->src[i].offset;
|
|
}
|
|
assert(scratch_reg != ~0u);
|
|
inst->src[i].nr = scratch_reg;
|
|
}
|
|
}
|
|
|
|
if (inst->dst.file == VGRF && inst->dst.nr == spill_reg_nr) {
|
|
emit_scratch_write(block, inst, spill_offset);
|
|
scratch_reg = inst->dst.nr;
|
|
}
|
|
}
|
|
|
|
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
|
|
}
|
|
|
|
} /* namespace brw */
|