332 lines
10 KiB
C++
332 lines
10 KiB
C++
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include "brw_vec4.h"
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#include "brw_vec4_live_variables.h"
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using namespace brw;
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#define MAX_INSTRUCTION (1 << 30)
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/** @file brw_vec4_live_variables.cpp
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*
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* Support for computing at the basic block level which variables
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* (virtual GRFs in our case) are live at entry and exit.
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*
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* See Muchnick's Advanced Compiler Design and Implementation, section
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* 14.1 (p444).
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*/
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/**
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* Sets up the use/def arrays and block-local approximation of the live ranges.
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*
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* The basic-block-level live variable analysis needs to know which
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* variables get used before they're completely defined, and which
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* variables are completely defined before they're used.
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*
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* We independently track each channel of a vec4. This is because we need to
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* be able to recognize a sequence like:
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*
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* ...
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* DP4 tmp.x a b;
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* DP4 tmp.y c d;
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* MUL result.xy tmp.xy e.xy
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* ...
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*
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* as having tmp live only across that sequence (assuming it's used nowhere
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* else), because it's a common pattern. A more conservative approach that
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* doesn't get tmp marked a deffed in this block will tend to result in
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* spilling.
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*/
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void
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vec4_live_variables::setup_def_use()
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{
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int ip = 0;
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foreach_block (block, cfg) {
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assert(ip == block->start_ip);
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if (block->num > 0)
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assert(cfg->blocks[block->num - 1]->end_ip == ip - 1);
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foreach_inst_in_block(vec4_instruction, inst, block) {
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struct block_data *bd = &block_data[block->num];
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/* Set up the instruction uses. */
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for (unsigned int i = 0; i < 3; i++) {
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if (inst->src[i].file == VGRF) {
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for (unsigned j = 0; j < DIV_ROUND_UP(inst->size_read(i), 16); j++) {
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for (int c = 0; c < 4; c++) {
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const unsigned v = var_from_reg(alloc, inst->src[i], c, j);
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start[v] = MIN2(start[v], ip);
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end[v] = ip;
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if (!BITSET_TEST(bd->def, v))
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BITSET_SET(bd->use, v);
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}
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}
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}
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}
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for (unsigned c = 0; c < 4; c++) {
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if (inst->reads_flag(c) &&
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!BITSET_TEST(bd->flag_def, c)) {
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BITSET_SET(bd->flag_use, c);
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}
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}
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/* Set up the instruction defs. */
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if (inst->dst.file == VGRF) {
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for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) {
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for (int c = 0; c < 4; c++) {
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if (inst->dst.writemask & (1 << c)) {
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const unsigned v = var_from_reg(alloc, inst->dst, c, i);
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start[v] = MIN2(start[v], ip);
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end[v] = ip;
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/* Check for unconditional register writes, these are the
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* things that screen off preceding definitions of a
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* variable, and thus qualify for being in def[].
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*/
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if ((!inst->predicate || inst->opcode == BRW_OPCODE_SEL) &&
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!BITSET_TEST(bd->use, v))
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BITSET_SET(bd->def, v);
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}
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}
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}
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}
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if (inst->writes_flag(devinfo)) {
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for (unsigned c = 0; c < 4; c++) {
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if ((inst->dst.writemask & (1 << c)) &&
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!BITSET_TEST(bd->flag_use, c)) {
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BITSET_SET(bd->flag_def, c);
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}
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}
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}
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ip++;
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}
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}
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}
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/**
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* The algorithm incrementally sets bits in liveout and livein,
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* propagating it through control flow. It will eventually terminate
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* because it only ever adds bits, and stops when no bits are added in
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* a pass.
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*/
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void
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vec4_live_variables::compute_live_variables()
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{
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bool cont = true;
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while (cont) {
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cont = false;
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foreach_block_reverse (block, cfg) {
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struct block_data *bd = &block_data[block->num];
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/* Update liveout */
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foreach_list_typed(bblock_link, child_link, link, &block->children) {
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struct block_data *child_bd = &block_data[child_link->block->num];
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_liveout = (child_bd->livein[i] &
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~bd->liveout[i]);
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if (new_liveout) {
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bd->liveout[i] |= new_liveout;
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cont = true;
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}
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}
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BITSET_WORD new_liveout = (child_bd->flag_livein[0] &
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~bd->flag_liveout[0]);
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if (new_liveout) {
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bd->flag_liveout[0] |= new_liveout;
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cont = true;
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}
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}
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/* Update livein */
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_livein = (bd->use[i] |
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(bd->liveout[i] &
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~bd->def[i]));
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if (new_livein & ~bd->livein[i]) {
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bd->livein[i] |= new_livein;
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cont = true;
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}
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}
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BITSET_WORD new_livein = (bd->flag_use[0] |
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(bd->flag_liveout[0] &
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~bd->flag_def[0]));
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if (new_livein & ~bd->flag_livein[0]) {
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bd->flag_livein[0] |= new_livein;
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cont = true;
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}
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}
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}
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}
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/**
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* Extend the start/end ranges for each variable to account for the
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* new information calculated from control flow.
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*/
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void
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vec4_live_variables::compute_start_end()
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{
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foreach_block (block, cfg) {
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const struct block_data &bd = block_data[block->num];
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for (int i = 0; i < num_vars; i++) {
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if (BITSET_TEST(bd.livein, i)) {
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start[i] = MIN2(start[i], block->start_ip);
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end[i] = MAX2(end[i], block->start_ip);
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}
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if (BITSET_TEST(bd.liveout, i)) {
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start[i] = MIN2(start[i], block->end_ip);
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end[i] = MAX2(end[i], block->end_ip);
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}
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}
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}
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}
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vec4_live_variables::vec4_live_variables(const backend_shader *s)
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: alloc(s->alloc), cfg(s->cfg)
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{
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mem_ctx = ralloc_context(NULL);
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num_vars = alloc.total_size * 8;
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start = ralloc_array(mem_ctx, int, num_vars);
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end = ralloc_array(mem_ctx, int, num_vars);
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for (int i = 0; i < num_vars; i++) {
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start[i] = MAX_INSTRUCTION;
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end[i] = -1;
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}
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devinfo = s->compiler->devinfo;
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block_data = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
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bitset_words = BITSET_WORDS(num_vars);
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for (int i = 0; i < cfg->num_blocks; i++) {
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block_data[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].flag_def[0] = 0;
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block_data[i].flag_use[0] = 0;
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block_data[i].flag_livein[0] = 0;
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block_data[i].flag_liveout[0] = 0;
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}
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setup_def_use();
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compute_live_variables();
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compute_start_end();
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}
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vec4_live_variables::~vec4_live_variables()
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{
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ralloc_free(mem_ctx);
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}
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static bool
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check_register_live_range(const vec4_live_variables *live, int ip,
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unsigned var, unsigned n)
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{
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for (unsigned j = 0; j < n; j += 4) {
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if (var + j >= unsigned(live->num_vars) ||
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live->start[var + j] > ip || live->end[var + j] < ip)
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return false;
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}
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return true;
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}
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bool
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vec4_live_variables::validate(const backend_shader *s) const
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{
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unsigned ip = 0;
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foreach_block_and_inst(block, vec4_instruction, inst, s->cfg) {
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for (unsigned c = 0; c < 4; c++) {
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if (inst->dst.writemask & (1 << c)) {
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for (unsigned i = 0; i < 3; i++) {
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if (inst->src[i].file == VGRF &&
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!check_register_live_range(this, ip,
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var_from_reg(alloc, inst->src[i], c),
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regs_read(inst, i)))
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return false;
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}
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if (inst->dst.file == VGRF &&
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!check_register_live_range(this, ip,
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var_from_reg(alloc, inst->dst, c),
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regs_written(inst)))
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return false;
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}
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}
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ip++;
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}
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return true;
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}
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int
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vec4_live_variables::var_range_start(unsigned v, unsigned n) const
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{
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int ip = INT_MAX;
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for (unsigned i = 0; i < n; i++)
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ip = MIN2(ip, start[v + i]);
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return ip;
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}
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int
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vec4_live_variables::var_range_end(unsigned v, unsigned n) const
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{
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int ip = INT_MIN;
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for (unsigned i = 0; i < n; i++)
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ip = MAX2(ip, end[v + i]);
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return ip;
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}
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bool
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vec4_live_variables::vgrfs_interfere(int a, int b) const
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{
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return !((var_range_end(8 * alloc.offsets[a], 8 * alloc.sizes[a]) <=
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var_range_start(8 * alloc.offsets[b], 8 * alloc.sizes[b])) ||
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(var_range_end(8 * alloc.offsets[b], 8 * alloc.sizes[b]) <=
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var_range_start(8 * alloc.offsets[a], 8 * alloc.sizes[a])));
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}
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