323 lines
11 KiB
C++
323 lines
11 KiB
C++
/*
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* Copyright © 2012, 2013, 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_vec4.h"
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#include "brw_vec4_live_variables.h"
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#include "brw_cfg.h"
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using namespace brw;
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/** @file brw_vec4_cse.cpp
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*
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* Support for local common subexpression elimination.
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*
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* See Muchnick's Advanced Compiler Design and Implementation, section
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* 13.1 (p378).
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*/
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namespace {
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struct aeb_entry : public exec_node {
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/** The instruction that generates the expression value. */
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vec4_instruction *generator;
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/** The temporary where the value is stored. */
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src_reg tmp;
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};
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}
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static bool
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is_expression(const vec4_instruction *const inst)
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{
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switch (inst->opcode) {
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case BRW_OPCODE_MOV:
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case BRW_OPCODE_SEL:
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case BRW_OPCODE_NOT:
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case BRW_OPCODE_AND:
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case BRW_OPCODE_OR:
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case BRW_OPCODE_XOR:
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case BRW_OPCODE_SHR:
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case BRW_OPCODE_SHL:
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case BRW_OPCODE_ASR:
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case BRW_OPCODE_CMP:
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case BRW_OPCODE_CMPN:
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case BRW_OPCODE_ADD:
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case BRW_OPCODE_MUL:
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case SHADER_OPCODE_MULH:
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case BRW_OPCODE_FRC:
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case BRW_OPCODE_RNDU:
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case BRW_OPCODE_RNDD:
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case BRW_OPCODE_RNDE:
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case BRW_OPCODE_RNDZ:
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case BRW_OPCODE_LINE:
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case BRW_OPCODE_PLN:
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case BRW_OPCODE_MAD:
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case BRW_OPCODE_LRP:
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case VEC4_OPCODE_UNPACK_UNIFORM:
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case SHADER_OPCODE_FIND_LIVE_CHANNEL:
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case SHADER_OPCODE_BROADCAST:
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case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
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case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
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return true;
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RSQ:
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case SHADER_OPCODE_SQRT:
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case SHADER_OPCODE_EXP2:
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case SHADER_OPCODE_LOG2:
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case SHADER_OPCODE_POW:
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case SHADER_OPCODE_INT_QUOTIENT:
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case SHADER_OPCODE_INT_REMAINDER:
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case SHADER_OPCODE_SIN:
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case SHADER_OPCODE_COS:
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return inst->mlen == 0;
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default:
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return false;
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}
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}
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static bool
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operands_match(const vec4_instruction *a, const vec4_instruction *b)
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{
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const src_reg *xs = a->src;
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const src_reg *ys = b->src;
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if (a->opcode == BRW_OPCODE_MAD) {
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return xs[0].equals(ys[0]) &&
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((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
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(xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
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} else if (a->opcode == BRW_OPCODE_MOV &&
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xs[0].file == IMM &&
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xs[0].type == BRW_REGISTER_TYPE_VF) {
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src_reg tmp_x = xs[0];
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src_reg tmp_y = ys[0];
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/* Smash out the values that are not part of the writemask. Otherwise
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* the equals operator will fail due to mismatches in unused components.
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*/
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const unsigned ab_writemask = a->dst.writemask & b->dst.writemask;
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const uint32_t mask = ((ab_writemask & WRITEMASK_X) ? 0x000000ff : 0) |
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((ab_writemask & WRITEMASK_Y) ? 0x0000ff00 : 0) |
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((ab_writemask & WRITEMASK_Z) ? 0x00ff0000 : 0) |
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((ab_writemask & WRITEMASK_W) ? 0xff000000 : 0);
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tmp_x.ud &= mask;
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tmp_y.ud &= mask;
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return tmp_x.equals(tmp_y);
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} else if (!a->is_commutative()) {
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return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
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} else {
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return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
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(xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
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}
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}
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/**
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* Checks if instructions match, exactly for sources, but loosely for
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* destination writemasks.
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*
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* \param 'a' is the generating expression from the AEB entry.
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* \param 'b' is the second occurrence of the expression that we're
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* considering eliminating.
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*/
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static bool
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instructions_match(vec4_instruction *a, vec4_instruction *b)
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{
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return a->opcode == b->opcode &&
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a->saturate == b->saturate &&
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a->predicate == b->predicate &&
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a->predicate_inverse == b->predicate_inverse &&
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a->conditional_mod == b->conditional_mod &&
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a->flag_subreg == b->flag_subreg &&
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a->dst.type == b->dst.type &&
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a->offset == b->offset &&
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a->mlen == b->mlen &&
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a->base_mrf == b->base_mrf &&
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a->header_size == b->header_size &&
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a->shadow_compare == b->shadow_compare &&
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((a->dst.writemask & b->dst.writemask) == a->dst.writemask) &&
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a->force_writemask_all == b->force_writemask_all &&
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a->size_written == b->size_written &&
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a->exec_size == b->exec_size &&
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a->group == b->group &&
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operands_match(a, b);
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}
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bool
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vec4_visitor::opt_cse_local(bblock_t *block, const vec4_live_variables &live)
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{
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bool progress = false;
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exec_list aeb;
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void *cse_ctx = ralloc_context(NULL);
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int ip = block->start_ip;
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foreach_inst_in_block (vec4_instruction, inst, block) {
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/* Skip some cases. */
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if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
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((inst->dst.file != ARF && inst->dst.file != FIXED_GRF) ||
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inst->dst.is_null()))
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{
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bool found = false;
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foreach_in_list_use_after(aeb_entry, entry, &aeb) {
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/* Match current instruction's expression against those in AEB. */
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if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
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instructions_match(inst, entry->generator)) {
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found = true;
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progress = true;
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break;
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}
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}
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if (!found) {
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if (inst->opcode != BRW_OPCODE_MOV ||
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(inst->opcode == BRW_OPCODE_MOV &&
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inst->src[0].file == IMM &&
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inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
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/* Our first sighting of this expression. Create an entry. */
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aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
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entry->tmp = src_reg(); /* file will be BAD_FILE */
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entry->generator = inst;
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aeb.push_tail(entry);
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}
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} else {
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/* This is at least our second sighting of this expression.
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* If we don't have a temporary already, make one.
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*/
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bool no_existing_temp = entry->tmp.file == BAD_FILE;
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if (no_existing_temp && !entry->generator->dst.is_null()) {
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entry->tmp = retype(src_reg(VGRF, alloc.allocate(
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regs_written(entry->generator)),
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NULL), inst->dst.type);
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const unsigned width = entry->generator->exec_size;
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unsigned component_size = width * type_sz(entry->tmp.type);
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unsigned num_copy_movs =
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DIV_ROUND_UP(entry->generator->size_written, component_size);
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for (unsigned i = 0; i < num_copy_movs; ++i) {
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vec4_instruction *copy =
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MOV(offset(entry->generator->dst, width, i),
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offset(entry->tmp, width, i));
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copy->exec_size = width;
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copy->group = entry->generator->group;
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copy->force_writemask_all =
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entry->generator->force_writemask_all;
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entry->generator->insert_after(block, copy);
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}
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entry->generator->dst = dst_reg(entry->tmp);
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}
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/* dest <- temp */
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if (!inst->dst.is_null()) {
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assert(inst->dst.type == entry->tmp.type);
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const unsigned width = inst->exec_size;
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unsigned component_size = width * type_sz(inst->dst.type);
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unsigned num_copy_movs =
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DIV_ROUND_UP(inst->size_written, component_size);
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for (unsigned i = 0; i < num_copy_movs; ++i) {
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vec4_instruction *copy =
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MOV(offset(inst->dst, width, i),
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offset(entry->tmp, width, i));
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copy->exec_size = inst->exec_size;
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copy->group = inst->group;
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copy->force_writemask_all = inst->force_writemask_all;
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inst->insert_before(block, copy);
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}
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}
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/* Set our iterator so that next time through the loop inst->next
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* will get the instruction in the basic block after the one we've
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* removed.
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*/
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vec4_instruction *prev = (vec4_instruction *)inst->prev;
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inst->remove(block);
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inst = prev;
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}
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}
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foreach_in_list_safe(aeb_entry, entry, &aeb) {
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/* Kill all AEB entries that write a different value to or read from
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* the flag register if we just wrote it.
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*/
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if (inst->writes_flag(devinfo)) {
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if (entry->generator->reads_flag() ||
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(entry->generator->writes_flag(devinfo) &&
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!instructions_match(inst, entry->generator))) {
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entry->remove();
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ralloc_free(entry);
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continue;
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}
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}
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for (int i = 0; i < 3; i++) {
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src_reg *src = &entry->generator->src[i];
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/* Kill all AEB entries that use the destination we just
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* overwrote.
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*/
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if (inst->dst.file == entry->generator->src[i].file &&
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inst->dst.nr == entry->generator->src[i].nr) {
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entry->remove();
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ralloc_free(entry);
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break;
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}
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/* Kill any AEB entries using registers that don't get reused any
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* more -- a sure sign they'll fail operands_match().
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*/
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if (src->file == VGRF) {
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if (live.var_range_end(var_from_reg(alloc, dst_reg(*src)), 8) < ip) {
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entry->remove();
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ralloc_free(entry);
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break;
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}
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}
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}
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}
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ip++;
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}
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ralloc_free(cse_ctx);
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return progress;
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}
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bool
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vec4_visitor::opt_cse()
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{
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bool progress = false;
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const vec4_live_variables &live = live_analysis.require();
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foreach_block (block, cfg) {
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progress = opt_cse_local(block, live) || progress;
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}
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if (progress)
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invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
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return progress;
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}
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