358 lines
12 KiB
C++
358 lines
12 KiB
C++
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef BRW_VEC4_H
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#define BRW_VEC4_H
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#include "brw_shader.h"
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#ifdef __cplusplus
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#include "brw_ir_vec4.h"
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#include "brw_ir_performance.h"
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#include "brw_vec4_builder.h"
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#include "brw_vec4_live_variables.h"
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#endif
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#include "compiler/glsl/ir.h"
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#include "compiler/nir/nir.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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const unsigned *
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brw_vec4_generate_assembly(const struct brw_compiler *compiler,
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void *log_data,
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void *mem_ctx,
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const nir_shader *nir,
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struct brw_vue_prog_data *prog_data,
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const struct cfg_t *cfg,
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const brw::performance &perf,
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struct brw_compile_stats *stats,
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bool debug_enabled);
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#ifdef __cplusplus
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} /* extern "C" */
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namespace brw {
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/**
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* The vertex shader front-end.
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*
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* Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
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* fixed-function) into VS IR.
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*/
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class vec4_visitor : public backend_shader
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{
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public:
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vec4_visitor(const struct brw_compiler *compiler,
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void *log_data,
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const struct brw_sampler_prog_key_data *key,
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struct brw_vue_prog_data *prog_data,
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const nir_shader *shader,
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void *mem_ctx,
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bool no_spills,
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bool debug_enabled);
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dst_reg dst_null_f()
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{
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return dst_reg(brw_null_reg());
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}
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dst_reg dst_null_df()
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{
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return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF));
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}
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dst_reg dst_null_d()
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{
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return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
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}
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dst_reg dst_null_ud()
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{
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return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
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}
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const struct brw_sampler_prog_key_data * const key_tex;
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struct brw_vue_prog_data * const prog_data;
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char *fail_msg;
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bool failed;
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/**
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* GLSL IR currently being processed, which is associated with our
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* driver IR instructions for debugging purposes.
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*/
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const void *base_ir;
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const char *current_annotation;
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int first_non_payload_grf;
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unsigned ubo_push_start[4];
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unsigned push_length;
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unsigned int max_grf;
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brw_analysis<brw::vec4_live_variables, backend_shader> live_analysis;
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brw_analysis<brw::performance, vec4_visitor> performance_analysis;
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bool need_all_constants_in_pull_buffer;
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/* Regs for vertex results. Generated at ir_variable visiting time
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* for the ir->location's used.
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*/
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dst_reg output_reg[VARYING_SLOT_TESS_MAX][4];
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unsigned output_num_components[VARYING_SLOT_TESS_MAX][4];
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const char *output_reg_annotation[VARYING_SLOT_TESS_MAX];
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int uniforms;
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src_reg shader_start_time;
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bool run();
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void fail(const char *msg, ...);
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int setup_uniforms(int payload_reg);
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bool reg_allocate_trivial();
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bool reg_allocate();
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void evaluate_spill_costs(float *spill_costs, bool *no_spill);
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int choose_spill_reg(struct ra_graph *g);
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void spill_reg(unsigned spill_reg);
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void move_grf_array_access_to_scratch();
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void move_uniform_array_access_to_pull_constants();
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void split_uniform_registers();
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void setup_push_ranges();
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virtual void invalidate_analysis(brw::analysis_dependency_class c);
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void split_virtual_grfs();
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bool opt_vector_float();
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bool opt_reduce_swizzle();
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bool dead_code_eliminate();
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bool opt_cmod_propagation();
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bool opt_copy_propagation(bool do_constant_prop = true);
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bool opt_cse_local(bblock_t *block, const vec4_live_variables &live);
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bool opt_cse();
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bool opt_algebraic();
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bool opt_register_coalesce();
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bool eliminate_find_live_channel();
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bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
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void opt_set_dependency_control();
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void opt_schedule_instructions();
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void convert_to_hw_regs();
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void fixup_3src_null_dest();
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bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
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bool lower_simd_width();
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bool scalarize_df();
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bool lower_64bit_mad_to_mul_add();
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void apply_logical_swizzle(struct brw_reg *hw_reg,
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vec4_instruction *inst, int arg);
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vec4_instruction *emit(vec4_instruction *inst);
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vec4_instruction *emit(enum opcode opcode);
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vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
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vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
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const src_reg &src0);
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vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
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const src_reg &src0, const src_reg &src1);
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vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
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const src_reg &src0, const src_reg &src1,
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const src_reg &src2);
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vec4_instruction *emit_before(bblock_t *block,
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vec4_instruction *inst,
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vec4_instruction *new_inst);
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#define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
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#define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
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#define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
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EMIT1(MOV)
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EMIT1(NOT)
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EMIT1(RNDD)
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EMIT1(RNDE)
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EMIT1(RNDZ)
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EMIT1(FRC)
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EMIT1(F32TO16)
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EMIT1(F16TO32)
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EMIT2(ADD)
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EMIT2(MUL)
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EMIT2(MACH)
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EMIT2(MAC)
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EMIT2(AND)
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EMIT2(OR)
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EMIT2(XOR)
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EMIT2(DP3)
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EMIT2(DP4)
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EMIT2(DPH)
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EMIT2(SHL)
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EMIT2(SHR)
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EMIT2(ASR)
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vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
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enum brw_conditional_mod condition);
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vec4_instruction *IF(src_reg src0, src_reg src1,
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enum brw_conditional_mod condition);
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vec4_instruction *IF(enum brw_predicate predicate);
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EMIT1(SCRATCH_READ)
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EMIT2(SCRATCH_WRITE)
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EMIT3(LRP)
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EMIT1(BFREV)
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EMIT3(BFE)
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EMIT2(BFI1)
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EMIT3(BFI2)
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EMIT1(FBH)
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EMIT1(FBL)
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EMIT1(CBIT)
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EMIT3(MAD)
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EMIT2(ADDC)
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EMIT2(SUBB)
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EMIT1(DIM)
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#undef EMIT1
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#undef EMIT2
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#undef EMIT3
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vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
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src_reg src0, src_reg src1);
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/**
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* Copy any live channel from \p src to the first channel of the
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* result.
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*/
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src_reg emit_uniformize(const src_reg &src);
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/** Fix all float operands of a 3-source instruction. */
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void fix_float_operands(src_reg op[3], nir_alu_instr *instr);
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src_reg fix_3src_operand(const src_reg &src);
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vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
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const src_reg &src1 = src_reg());
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src_reg fix_math_operand(const src_reg &src);
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void emit_pack_half_2x16(dst_reg dst, src_reg src0);
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void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
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void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
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void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
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void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
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void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
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src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
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src_reg surface);
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void emit_ndc_computation();
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void emit_psiz_and_flags(dst_reg reg);
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vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying, int comp);
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virtual void emit_urb_slot(dst_reg reg, int varying);
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src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
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src_reg *reladdr, int reg_offset);
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void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
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dst_reg dst,
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src_reg orig_src,
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int base_offset);
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void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
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int base_offset);
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void emit_pull_constant_load_reg(dst_reg dst,
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src_reg surf_index,
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src_reg offset,
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bblock_t *before_block,
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vec4_instruction *before_inst);
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src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
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vec4_instruction *inst, src_reg src);
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void resolve_ud_negate(src_reg *reg);
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bool lower_minmax();
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src_reg get_timestamp();
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void dump_instruction(const backend_instruction *inst) const;
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void dump_instruction(const backend_instruction *inst, FILE *file) const;
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bool optimize_predicate(nir_alu_instr *instr, enum brw_predicate *predicate);
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void emit_conversion_from_double(dst_reg dst, src_reg src);
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void emit_conversion_to_double(dst_reg dst, src_reg src);
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vec4_instruction *shuffle_64bit_data(dst_reg dst, src_reg src,
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bool for_write,
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bool for_scratch = false,
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bblock_t *block = NULL,
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vec4_instruction *ref = NULL);
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virtual void emit_nir_code();
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virtual void nir_setup_uniforms();
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virtual void nir_emit_impl(nir_function_impl *impl);
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virtual void nir_emit_cf_list(exec_list *list);
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virtual void nir_emit_if(nir_if *if_stmt);
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virtual void nir_emit_loop(nir_loop *loop);
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virtual void nir_emit_block(nir_block *block);
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virtual void nir_emit_instr(nir_instr *instr);
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virtual void nir_emit_load_const(nir_load_const_instr *instr);
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src_reg get_nir_ssbo_intrinsic_index(nir_intrinsic_instr *instr);
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virtual void nir_emit_intrinsic(nir_intrinsic_instr *instr);
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virtual void nir_emit_alu(nir_alu_instr *instr);
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virtual void nir_emit_jump(nir_jump_instr *instr);
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virtual void nir_emit_texture(nir_tex_instr *instr);
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virtual void nir_emit_undef(nir_ssa_undef_instr *instr);
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virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr);
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dst_reg get_nir_dest(const nir_dest &dest, enum brw_reg_type type);
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dst_reg get_nir_dest(const nir_dest &dest, nir_alu_type type);
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dst_reg get_nir_dest(const nir_dest &dest);
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src_reg get_nir_src(const nir_src &src, enum brw_reg_type type,
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unsigned num_components = 4);
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src_reg get_nir_src(const nir_src &src, nir_alu_type type,
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unsigned num_components = 4);
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src_reg get_nir_src(const nir_src &src,
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unsigned num_components = 4);
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src_reg get_nir_src_imm(const nir_src &src);
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src_reg get_indirect_offset(nir_intrinsic_instr *instr);
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dst_reg *nir_locals;
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dst_reg *nir_ssa_values;
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protected:
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void emit_vertex();
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void setup_payload_interference(struct ra_graph *g, int first_payload_node,
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int reg_node_count);
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virtual void setup_payload() = 0;
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virtual void emit_prolog() = 0;
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virtual void emit_thread_end() = 0;
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virtual void emit_urb_write_header(int mrf) = 0;
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virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
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virtual void gs_emit_vertex(int stream_id);
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virtual void gs_end_primitive();
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private:
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/**
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* If true, then register allocation should fail instead of spilling.
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*/
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const bool no_spills;
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unsigned last_scratch; /**< measured in 32-byte (register size) units */
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};
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} /* namespace brw */
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#endif /* __cplusplus */
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#endif /* BRW_VEC4_H */
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