201 lines
6.3 KiB
C
201 lines
6.3 KiB
C
/*
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* Copyright © 2021 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_private.h"
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#include "compiler/shader_info.h"
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#include "intel/dev/intel_debug.h"
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#include "intel/dev/intel_device_info.h"
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#include "util/ralloc.h"
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unsigned
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brw_required_dispatch_width(const struct shader_info *info)
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{
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if ((int)info->subgroup_size >= (int)SUBGROUP_SIZE_REQUIRE_8) {
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assert(gl_shader_stage_uses_workgroup(info->stage));
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/* These enum values are expressly chosen to be equal to the subgroup
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* size that they require.
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*/
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return (unsigned)info->subgroup_size;
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} else {
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return 0;
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}
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}
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static inline bool
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test_bit(unsigned mask, unsigned bit) {
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return mask & (1u << bit);
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}
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bool
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brw_simd_should_compile(void *mem_ctx,
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unsigned simd,
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const struct intel_device_info *devinfo,
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struct brw_cs_prog_data *prog_data,
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unsigned required,
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const char **error)
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{
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assert(!test_bit(prog_data->prog_mask, simd));
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assert(error);
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const unsigned width = 8u << simd;
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/* For shaders with variable size workgroup, we will always compile all the
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* variants, since the choice will happen only at dispatch time.
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*/
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const bool workgroup_size_variable = prog_data->local_size[0] == 0;
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if (!workgroup_size_variable) {
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if (test_bit(prog_data->prog_spilled, simd)) {
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*error = ralloc_asprintf(
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mem_ctx, "SIMD%u skipped because would spill", width);
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return false;
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}
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const unsigned workgroup_size = prog_data->local_size[0] *
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prog_data->local_size[1] *
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prog_data->local_size[2];
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unsigned max_threads = devinfo->max_cs_workgroup_threads;
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if (required && required != width) {
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*error = ralloc_asprintf(
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mem_ctx, "SIMD%u skipped because required dispatch width is %u",
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width, required);
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return false;
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}
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if (simd > 0 && test_bit(prog_data->prog_mask, simd - 1) &&
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workgroup_size <= (width / 2)) {
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*error = ralloc_asprintf(
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mem_ctx, "SIMD%u skipped because workgroup size %u already fits in SIMD%u",
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width, workgroup_size, width / 2);
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return false;
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}
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if (DIV_ROUND_UP(workgroup_size, width) > max_threads) {
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*error = ralloc_asprintf(
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mem_ctx, "SIMD%u can't fit all %u invocations in %u threads",
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width, workgroup_size, max_threads);
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return false;
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}
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/* The SIMD32 is only enabled for cases it is needed unless forced.
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*
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* TODO: Use performance_analysis and drop this rule.
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*/
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if (width == 32) {
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if (!INTEL_DEBUG(DEBUG_DO32) && prog_data->prog_mask) {
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*error = ralloc_strdup(
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mem_ctx, "SIMD32 skipped because not required");
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return false;
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}
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}
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}
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const bool env_skip[3] = {
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INTEL_DEBUG(DEBUG_NO8),
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INTEL_DEBUG(DEBUG_NO16),
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INTEL_DEBUG(DEBUG_NO32),
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};
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if (unlikely(env_skip[simd])) {
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*error = ralloc_asprintf(
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mem_ctx, "SIMD%u skipped because INTEL_DEBUG=no%u",
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width, width);
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return false;
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}
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return true;
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}
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void
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brw_simd_mark_compiled(unsigned simd, struct brw_cs_prog_data *prog_data, bool spilled)
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{
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assert(!test_bit(prog_data->prog_mask, simd));
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prog_data->prog_mask |= 1u << simd;
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/* If a SIMD spilled, all the larger ones would spill too. */
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if (spilled) {
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for (unsigned i = simd; i < 3; i++)
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prog_data->prog_spilled |= 1u << i;
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}
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}
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int
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brw_simd_select(const struct brw_cs_prog_data *prog_data)
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{
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assert((prog_data->prog_mask & ~0x7u) == 0);
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const unsigned not_spilled_mask =
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prog_data->prog_mask & ~prog_data->prog_spilled;
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/* Util functions index bits from 1 instead of 0, adjust before return. */
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if (not_spilled_mask)
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return util_last_bit(not_spilled_mask) - 1;
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else if (prog_data->prog_mask)
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return ffs(prog_data->prog_mask) - 1;
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else
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return -1;
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}
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int
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brw_simd_select_for_workgroup_size(const struct intel_device_info *devinfo,
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const struct brw_cs_prog_data *prog_data,
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const unsigned *sizes)
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{
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assert(sizes);
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if (prog_data->local_size[0] == sizes[0] &&
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prog_data->local_size[1] == sizes[1] &&
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prog_data->local_size[2] == sizes[2])
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return brw_simd_select(prog_data);
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void *mem_ctx = ralloc_context(NULL);
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struct brw_cs_prog_data cloned = *prog_data;
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for (unsigned i = 0; i < 3; i++)
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cloned.local_size[i] = sizes[i];
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cloned.prog_mask = 0;
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cloned.prog_spilled = 0;
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const char *error[3] = {0};
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for (unsigned simd = 0; simd < 3; simd++) {
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/* We are not recompiling, so use original results of prog_mask and
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* prog_spilled as they will already contain all possible compilations.
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*/
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if (brw_simd_should_compile(mem_ctx, simd, devinfo, &cloned,
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0 /* required_dispatch_width */, &error[simd]) &&
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test_bit(prog_data->prog_mask, simd)) {
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brw_simd_mark_compiled(simd, &cloned, test_bit(prog_data->prog_spilled, simd));
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}
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}
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ralloc_free(mem_ctx);
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return brw_simd_select(&cloned);
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}
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