197 lines
5.9 KiB
C++
197 lines
5.9 KiB
C++
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef BRW_SHADER_H
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#define BRW_SHADER_H
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#include <stdint.h>
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#include "brw_cfg.h"
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#include "brw_compiler.h"
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#include "compiler/nir/nir.h"
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#ifdef __cplusplus
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#include "brw_ir_analysis.h"
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#include "brw_ir_allocator.h"
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enum instruction_scheduler_mode {
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SCHEDULE_PRE,
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SCHEDULE_PRE_NON_LIFO,
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SCHEDULE_PRE_LIFO,
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SCHEDULE_POST,
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SCHEDULE_NONE,
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};
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#define UBO_START ((1 << 16) - 4)
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struct backend_shader {
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protected:
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backend_shader(const struct brw_compiler *compiler,
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void *log_data,
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void *mem_ctx,
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const nir_shader *shader,
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struct brw_stage_prog_data *stage_prog_data,
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bool debug_enabled);
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public:
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virtual ~backend_shader();
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const struct brw_compiler *compiler;
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void *log_data; /* Passed to compiler->*_log functions */
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const struct intel_device_info * const devinfo;
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const nir_shader *nir;
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struct brw_stage_prog_data * const stage_prog_data;
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/** ralloc context for temporary data used during compile */
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void *mem_ctx;
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/**
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* List of either fs_inst or vec4_instruction (inheriting from
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* backend_instruction)
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*/
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exec_list instructions;
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cfg_t *cfg;
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brw_analysis<brw::idom_tree, backend_shader> idom_analysis;
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gl_shader_stage stage;
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bool debug_enabled;
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const char *stage_name;
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const char *stage_abbrev;
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brw::simple_allocator alloc;
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virtual void dump_instruction(const backend_instruction *inst) const = 0;
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virtual void dump_instruction(const backend_instruction *inst, FILE *file) const = 0;
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virtual void dump_instructions() const;
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virtual void dump_instructions(const char *name) const;
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void calculate_cfg();
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virtual void invalidate_analysis(brw::analysis_dependency_class c);
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};
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#else
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struct backend_shader;
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#endif /* __cplusplus */
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enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
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enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
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uint32_t brw_math_function(enum opcode op);
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const char *brw_instruction_name(const struct brw_isa_info *isa,
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enum opcode op);
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bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
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bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
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bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
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bool opt_predicated_break(struct backend_shader *s);
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* brw_fs_reg_allocate.cpp */
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void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
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/* brw_vec4_reg_allocate.cpp */
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void brw_vec4_alloc_reg_set(struct brw_compiler *compiler);
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/* brw_disasm.c */
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extern const char *const conditional_modifier[16];
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extern const char *const pred_ctrl_align16[16];
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/* Per-thread scratch space is a power-of-two multiple of 1KB. */
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static inline unsigned
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brw_get_scratch_size(int size)
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{
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return MAX2(1024, util_next_power_of_two(size));
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}
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static inline nir_variable_mode
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brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
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gl_shader_stage stage)
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{
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const struct intel_device_info *devinfo = compiler->devinfo;
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const bool is_scalar = compiler->scalar_stage[stage];
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nir_variable_mode indirect_mask = (nir_variable_mode) 0;
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switch (stage) {
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case MESA_SHADER_VERTEX:
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case MESA_SHADER_FRAGMENT:
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indirect_mask |= nir_var_shader_in;
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break;
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case MESA_SHADER_GEOMETRY:
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if (!is_scalar)
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indirect_mask |= nir_var_shader_in;
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break;
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default:
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/* Everything else can handle indirect inputs */
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break;
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}
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if (is_scalar && stage != MESA_SHADER_TESS_CTRL &&
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stage != MESA_SHADER_TASK &&
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stage != MESA_SHADER_MESH)
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indirect_mask |= nir_var_shader_out;
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/* On HSW+, we allow indirects in scalar shaders. They get implemented
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* using nir_lower_vars_to_explicit_types and nir_lower_explicit_io in
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* brw_postprocess_nir.
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*
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* We haven't plumbed through the indirect scratch messages on gfx6 or
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* earlier so doing indirects via scratch doesn't work there. On gfx7 and
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* earlier the scratch space size is limited to 12kB. If we allowed
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* indirects as scratch all the time, we may easily exceed this limit
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* without having any fallback.
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*/
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if (is_scalar && devinfo->verx10 <= 70)
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indirect_mask |= nir_var_function_temp;
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return indirect_mask;
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}
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bool brw_texture_offset(const nir_tex_instr *tex, unsigned src,
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uint32_t *offset_bits);
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/**
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* Scratch data used when compiling a GLSL geometry shader.
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*/
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struct brw_gs_compile
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{
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struct brw_gs_prog_key key;
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struct brw_vue_map input_vue_map;
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unsigned control_data_bits_per_vertex;
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unsigned control_data_header_size_bits;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* BRW_SHADER_H */
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