1272 lines
33 KiB
C
1272 lines
33 KiB
C
/*
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Copyright (C) Intel Corp. 2006. All Rights Reserved.
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Intel funded Tungsten Graphics to
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develop this 3D driver.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**********************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keithw@vmware.com>
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*/
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/** @file brw_reg.h
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*
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* This file defines struct brw_reg, which is our representation for EU
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* registers. They're not a hardware specific format, just an abstraction
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* that intends to capture the full flexibility of the hardware registers.
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*
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* The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
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* the abstract brw_reg type into the actual hardware instruction encoding.
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*/
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#ifndef BRW_REG_H
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#define BRW_REG_H
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#include <stdbool.h>
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#include "util/compiler.h"
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#include "main/macros.h"
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#include "program/prog_instruction.h"
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#include "brw_eu_defines.h"
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#include "brw_reg_type.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct intel_device_info;
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/** Number of general purpose registers (VS, WM, etc) */
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#define BRW_MAX_GRF 128
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/**
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* First GRF used for the MRF hack.
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*
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* On gfx7, MRFs are no longer used, and contiguous GRFs are used instead. We
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* haven't converted our compiler to be aware of this, so it asks for MRFs and
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* brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
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* register allocators have to be careful of this to avoid corrupting the "MRF"s
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* with actual GRF allocations.
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*/
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#define GFX7_MRF_HACK_START 112
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/** Number of message register file registers */
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#define BRW_MAX_MRF(gen) (gen == 6 ? 24 : 16)
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#define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
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#define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
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#define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
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#define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
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#define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
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#define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
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#define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
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#define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
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#define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
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#define BRW_SWIZZLE_YXYX BRW_SWIZZLE4(1,0,1,0)
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#define BRW_SWIZZLE_XZXZ BRW_SWIZZLE4(0,2,0,2)
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#define BRW_SWIZZLE_YZXW BRW_SWIZZLE4(1,2,0,3)
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#define BRW_SWIZZLE_YWYW BRW_SWIZZLE4(1,3,1,3)
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#define BRW_SWIZZLE_ZXYW BRW_SWIZZLE4(2,0,1,3)
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#define BRW_SWIZZLE_ZWZW BRW_SWIZZLE4(2,3,2,3)
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#define BRW_SWIZZLE_WZWZ BRW_SWIZZLE4(3,2,3,2)
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#define BRW_SWIZZLE_WZYX BRW_SWIZZLE4(3,2,1,0)
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#define BRW_SWIZZLE_XXZZ BRW_SWIZZLE4(0,0,2,2)
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#define BRW_SWIZZLE_YYWW BRW_SWIZZLE4(1,1,3,3)
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#define BRW_SWIZZLE_YXWZ BRW_SWIZZLE4(1,0,3,2)
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#define BRW_SWZ_COMP_INPUT(comp) (BRW_SWIZZLE_XYZW >> ((comp)*2))
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#define BRW_SWZ_COMP_OUTPUT(comp) (BRW_SWIZZLE_XYZW << ((comp)*2))
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static inline bool
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brw_is_single_value_swizzle(unsigned swiz)
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{
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return (swiz == BRW_SWIZZLE_XXXX ||
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swiz == BRW_SWIZZLE_YYYY ||
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swiz == BRW_SWIZZLE_ZZZZ ||
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swiz == BRW_SWIZZLE_WWWW);
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}
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/**
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* Compute the swizzle obtained from the application of \p swz0 on the result
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* of \p swz1. The argument ordering is expected to match function
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* composition.
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*/
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static inline unsigned
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brw_compose_swizzle(unsigned swz0, unsigned swz1)
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{
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return BRW_SWIZZLE4(
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BRW_GET_SWZ(swz1, BRW_GET_SWZ(swz0, 0)),
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BRW_GET_SWZ(swz1, BRW_GET_SWZ(swz0, 1)),
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BRW_GET_SWZ(swz1, BRW_GET_SWZ(swz0, 2)),
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BRW_GET_SWZ(swz1, BRW_GET_SWZ(swz0, 3)));
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}
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/**
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* Return the result of applying swizzle \p swz to shuffle the bits of \p mask
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* (AKA image).
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*/
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static inline unsigned
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brw_apply_swizzle_to_mask(unsigned swz, unsigned mask)
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{
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unsigned result = 0;
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for (unsigned i = 0; i < 4; i++) {
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if (mask & (1 << BRW_GET_SWZ(swz, i)))
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result |= 1 << i;
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}
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return result;
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}
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/**
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* Return the result of applying the inverse of swizzle \p swz to shuffle the
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* bits of \p mask (AKA preimage). Useful to find out which components are
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* read from a swizzled source given the instruction writemask.
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*/
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static inline unsigned
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brw_apply_inv_swizzle_to_mask(unsigned swz, unsigned mask)
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{
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unsigned result = 0;
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for (unsigned i = 0; i < 4; i++) {
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if (mask & (1 << i))
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result |= 1 << BRW_GET_SWZ(swz, i);
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}
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return result;
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}
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/**
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* Construct an identity swizzle for the set of enabled channels given by \p
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* mask. The result will only reference channels enabled in the provided \p
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* mask, assuming that \p mask is non-zero. The constructed swizzle will
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* satisfy the property that for any instruction OP and any mask:
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*
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* brw_OP(p, brw_writemask(dst, mask),
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* brw_swizzle(src, brw_swizzle_for_mask(mask)));
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*
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* will be equivalent to the same instruction without swizzle:
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*
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* brw_OP(p, brw_writemask(dst, mask), src);
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*/
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static inline unsigned
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brw_swizzle_for_mask(unsigned mask)
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{
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unsigned last = (mask ? ffs(mask) - 1 : 0);
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unsigned swz[4];
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for (unsigned i = 0; i < 4; i++)
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last = swz[i] = (mask & (1 << i) ? i : last);
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return BRW_SWIZZLE4(swz[0], swz[1], swz[2], swz[3]);
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}
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/**
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* Construct an identity swizzle for the first \p n components of a vector.
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* When only a subset of channels of a vec4 are used we don't want to
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* reference the other channels, as that will tell optimization passes that
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* those other channels are used.
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*/
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static inline unsigned
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brw_swizzle_for_size(unsigned n)
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{
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return brw_swizzle_for_mask((1 << n) - 1);
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}
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/**
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* Converse of brw_swizzle_for_mask(). Returns the mask of components
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* accessed by the specified swizzle \p swz.
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*/
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static inline unsigned
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brw_mask_for_swizzle(unsigned swz)
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{
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return brw_apply_inv_swizzle_to_mask(swz, ~0);
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}
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uint32_t brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz);
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#define REG_SIZE (8*4)
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/* These aren't hardware structs, just something useful for us to pass around:
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*
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* Align1 operation has a lot of control over input ranges. Used in
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* WM programs to implement shaders decomposed into "channel serial"
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* or "structure of array" form:
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*/
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struct brw_reg {
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union {
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struct {
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enum brw_reg_type type:4;
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enum brw_reg_file file:3; /* :2 hardware format */
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unsigned negate:1; /* source only */
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unsigned abs:1; /* source only */
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unsigned address_mode:1; /* relative addressing, hopefully! */
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unsigned pad0:17;
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unsigned subnr:5; /* :1 in align16 */
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};
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uint32_t bits;
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};
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union {
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struct {
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unsigned nr;
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unsigned swizzle:8; /* src only, align16 only */
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unsigned writemask:4; /* dest only, align16 only */
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int indirect_offset:10; /* relative addressing offset */
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unsigned vstride:4; /* source only */
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unsigned width:3; /* src only, align1 only */
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unsigned hstride:2; /* align1 only */
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unsigned pad1:1;
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};
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double df;
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uint64_t u64;
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int64_t d64;
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float f;
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int d;
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unsigned ud;
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};
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};
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static inline bool
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brw_regs_equal(const struct brw_reg *a, const struct brw_reg *b)
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{
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return a->bits == b->bits && a->u64 == b->u64;
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}
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static inline bool
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brw_regs_negative_equal(const struct brw_reg *a, const struct brw_reg *b)
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{
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if (a->file == IMM) {
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if (a->bits != b->bits)
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return false;
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switch ((enum brw_reg_type) a->type) {
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case BRW_REGISTER_TYPE_UQ:
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case BRW_REGISTER_TYPE_Q:
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return a->d64 == -b->d64;
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case BRW_REGISTER_TYPE_DF:
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return a->df == -b->df;
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case BRW_REGISTER_TYPE_UD:
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case BRW_REGISTER_TYPE_D:
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return a->d == -b->d;
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case BRW_REGISTER_TYPE_F:
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return a->f == -b->f;
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case BRW_REGISTER_TYPE_VF:
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/* It is tempting to treat 0 as a negation of 0 (and -0 as a negation
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* of -0). There are occasions where 0 or -0 is used and the exact
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* bit pattern is desired. At the very least, changing this to allow
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* 0 as a negation of 0 causes some fp64 tests to fail on IVB.
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*/
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return a->ud == (b->ud ^ 0x80808080);
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case BRW_REGISTER_TYPE_UW:
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case BRW_REGISTER_TYPE_W:
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case BRW_REGISTER_TYPE_UV:
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case BRW_REGISTER_TYPE_V:
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case BRW_REGISTER_TYPE_HF:
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/* FINISHME: Implement support for these types once there is
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* something in the compiler that can generate them. Until then,
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* they cannot be tested.
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*/
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return false;
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case BRW_REGISTER_TYPE_UB:
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case BRW_REGISTER_TYPE_B:
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case BRW_REGISTER_TYPE_NF:
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default:
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unreachable("not reached");
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}
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} else {
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struct brw_reg tmp = *a;
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tmp.negate = !tmp.negate;
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return brw_regs_equal(&tmp, b);
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}
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}
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struct brw_indirect {
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unsigned addr_subnr:4;
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int addr_offset:10;
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unsigned pad:18;
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};
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static inline unsigned
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type_sz(unsigned type)
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{
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switch(type) {
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case BRW_REGISTER_TYPE_UQ:
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case BRW_REGISTER_TYPE_Q:
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case BRW_REGISTER_TYPE_DF:
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case BRW_REGISTER_TYPE_NF:
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return 8;
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case BRW_REGISTER_TYPE_UD:
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case BRW_REGISTER_TYPE_D:
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case BRW_REGISTER_TYPE_F:
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case BRW_REGISTER_TYPE_VF:
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return 4;
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case BRW_REGISTER_TYPE_UW:
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case BRW_REGISTER_TYPE_W:
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case BRW_REGISTER_TYPE_HF:
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/* [U]V components are 4-bit, but HW unpacks them to 16-bit (2 bytes) */
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case BRW_REGISTER_TYPE_UV:
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case BRW_REGISTER_TYPE_V:
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return 2;
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case BRW_REGISTER_TYPE_UB:
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case BRW_REGISTER_TYPE_B:
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return 1;
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default:
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unreachable("not reached");
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}
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}
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static inline enum brw_reg_type
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get_exec_type(const enum brw_reg_type type)
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{
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switch (type) {
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case BRW_REGISTER_TYPE_B:
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case BRW_REGISTER_TYPE_V:
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return BRW_REGISTER_TYPE_W;
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case BRW_REGISTER_TYPE_UB:
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case BRW_REGISTER_TYPE_UV:
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return BRW_REGISTER_TYPE_UW;
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case BRW_REGISTER_TYPE_VF:
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return BRW_REGISTER_TYPE_F;
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default:
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return type;
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}
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}
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/**
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* Return an integer type of the requested size and signedness.
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*/
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static inline enum brw_reg_type
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brw_int_type(unsigned sz, bool is_signed)
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{
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switch (sz) {
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case 1:
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return (is_signed ? BRW_REGISTER_TYPE_B : BRW_REGISTER_TYPE_UB);
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case 2:
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return (is_signed ? BRW_REGISTER_TYPE_W : BRW_REGISTER_TYPE_UW);
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case 4:
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return (is_signed ? BRW_REGISTER_TYPE_D : BRW_REGISTER_TYPE_UD);
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case 8:
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return (is_signed ? BRW_REGISTER_TYPE_Q : BRW_REGISTER_TYPE_UQ);
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default:
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unreachable("Not reached.");
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}
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}
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/**
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* Construct a brw_reg.
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* \param file one of the BRW_x_REGISTER_FILE values
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* \param nr register number/index
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* \param subnr register sub number
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* \param negate register negate modifier
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* \param abs register abs modifier
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* \param type one of BRW_REGISTER_TYPE_x
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* \param vstride one of BRW_VERTICAL_STRIDE_x
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* \param width one of BRW_WIDTH_x
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* \param hstride one of BRW_HORIZONTAL_STRIDE_x
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* \param swizzle one of BRW_SWIZZLE_x
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* \param writemask WRITEMASK_X/Y/Z/W bitfield
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*/
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static inline struct brw_reg
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brw_reg(enum brw_reg_file file,
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unsigned nr,
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unsigned subnr,
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unsigned negate,
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unsigned abs,
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enum brw_reg_type type,
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unsigned vstride,
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unsigned width,
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unsigned hstride,
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unsigned swizzle,
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unsigned writemask)
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{
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struct brw_reg reg;
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if (file == BRW_GENERAL_REGISTER_FILE)
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assert(nr < BRW_MAX_GRF);
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else if (file == BRW_ARCHITECTURE_REGISTER_FILE)
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assert(nr <= BRW_ARF_TIMESTAMP);
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/* Asserting on the MRF register number requires to know the hardware gen
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* (gfx6 has 24 MRF registers), which we don't know here, so we assert
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* for that in the generators and in brw_eu_emit.c
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*/
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reg.type = type;
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reg.file = file;
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reg.negate = negate;
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reg.abs = abs;
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reg.address_mode = BRW_ADDRESS_DIRECT;
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reg.pad0 = 0;
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reg.subnr = subnr * type_sz(type);
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reg.nr = nr;
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/* Could do better: If the reg is r5.3<0;1,0>, we probably want to
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* set swizzle and writemask to W, as the lower bits of subnr will
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* be lost when converted to align16. This is probably too much to
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* keep track of as you'd want it adjusted by suboffset(), etc.
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* Perhaps fix up when converting to align16?
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*/
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reg.swizzle = swizzle;
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reg.writemask = writemask;
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reg.indirect_offset = 0;
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reg.vstride = vstride;
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reg.width = width;
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reg.hstride = hstride;
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reg.pad1 = 0;
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return reg;
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}
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/** Construct float[16] register */
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static inline struct brw_reg
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brw_vec16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
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{
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return brw_reg(file,
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nr,
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subnr,
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0,
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0,
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BRW_REGISTER_TYPE_F,
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BRW_VERTICAL_STRIDE_16,
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BRW_WIDTH_16,
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BRW_HORIZONTAL_STRIDE_1,
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BRW_SWIZZLE_XYZW,
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WRITEMASK_XYZW);
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}
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/** Construct float[8] register */
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static inline struct brw_reg
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brw_vec8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
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{
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return brw_reg(file,
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nr,
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subnr,
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0,
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0,
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BRW_REGISTER_TYPE_F,
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BRW_VERTICAL_STRIDE_8,
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BRW_WIDTH_8,
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BRW_HORIZONTAL_STRIDE_1,
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BRW_SWIZZLE_XYZW,
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WRITEMASK_XYZW);
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}
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/** Construct float[4] register */
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static inline struct brw_reg
|
|
brw_vec4_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_reg(file,
|
|
nr,
|
|
subnr,
|
|
0,
|
|
0,
|
|
BRW_REGISTER_TYPE_F,
|
|
BRW_VERTICAL_STRIDE_4,
|
|
BRW_WIDTH_4,
|
|
BRW_HORIZONTAL_STRIDE_1,
|
|
BRW_SWIZZLE_XYZW,
|
|
WRITEMASK_XYZW);
|
|
}
|
|
|
|
/** Construct float[2] register */
|
|
static inline struct brw_reg
|
|
brw_vec2_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_reg(file,
|
|
nr,
|
|
subnr,
|
|
0,
|
|
0,
|
|
BRW_REGISTER_TYPE_F,
|
|
BRW_VERTICAL_STRIDE_2,
|
|
BRW_WIDTH_2,
|
|
BRW_HORIZONTAL_STRIDE_1,
|
|
BRW_SWIZZLE_XYXY,
|
|
WRITEMASK_XY);
|
|
}
|
|
|
|
/** Construct float[1] register */
|
|
static inline struct brw_reg
|
|
brw_vec1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_reg(file,
|
|
nr,
|
|
subnr,
|
|
0,
|
|
0,
|
|
BRW_REGISTER_TYPE_F,
|
|
BRW_VERTICAL_STRIDE_0,
|
|
BRW_WIDTH_1,
|
|
BRW_HORIZONTAL_STRIDE_0,
|
|
BRW_SWIZZLE_XXXX,
|
|
WRITEMASK_X);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_vecn_reg(unsigned width, enum brw_reg_file file,
|
|
unsigned nr, unsigned subnr)
|
|
{
|
|
switch (width) {
|
|
case 1:
|
|
return brw_vec1_reg(file, nr, subnr);
|
|
case 2:
|
|
return brw_vec2_reg(file, nr, subnr);
|
|
case 4:
|
|
return brw_vec4_reg(file, nr, subnr);
|
|
case 8:
|
|
return brw_vec8_reg(file, nr, subnr);
|
|
case 16:
|
|
return brw_vec16_reg(file, nr, subnr);
|
|
default:
|
|
unreachable("Invalid register width");
|
|
}
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
retype(struct brw_reg reg, enum brw_reg_type type)
|
|
{
|
|
reg.type = type;
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
firsthalf(struct brw_reg reg)
|
|
{
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
sechalf(struct brw_reg reg)
|
|
{
|
|
if (reg.vstride)
|
|
reg.nr++;
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
offset(struct brw_reg reg, unsigned delta)
|
|
{
|
|
reg.nr += delta;
|
|
return reg;
|
|
}
|
|
|
|
|
|
static inline struct brw_reg
|
|
byte_offset(struct brw_reg reg, unsigned bytes)
|
|
{
|
|
unsigned newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
|
|
reg.nr = newoffset / REG_SIZE;
|
|
reg.subnr = newoffset % REG_SIZE;
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
suboffset(struct brw_reg reg, unsigned delta)
|
|
{
|
|
return byte_offset(reg, delta * type_sz(reg.type));
|
|
}
|
|
|
|
/** Construct unsigned word[16] register */
|
|
static inline struct brw_reg
|
|
brw_uw16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
|
|
{
|
|
return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
|
|
}
|
|
|
|
/** Construct unsigned word[8] register */
|
|
static inline struct brw_reg
|
|
brw_uw8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
|
|
{
|
|
return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
|
|
}
|
|
|
|
/** Construct unsigned word[1] register */
|
|
static inline struct brw_reg
|
|
brw_uw1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
|
|
{
|
|
return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_ud1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
|
|
{
|
|
return retype(brw_vec1_reg(file, nr, subnr), BRW_REGISTER_TYPE_UD);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_imm_reg(enum brw_reg_type type)
|
|
{
|
|
return brw_reg(BRW_IMMEDIATE_VALUE,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
type,
|
|
BRW_VERTICAL_STRIDE_0,
|
|
BRW_WIDTH_1,
|
|
BRW_HORIZONTAL_STRIDE_0,
|
|
0,
|
|
0);
|
|
}
|
|
|
|
/** Construct float immediate register */
|
|
static inline struct brw_reg
|
|
brw_imm_df(double df)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_DF);
|
|
imm.df = df;
|
|
return imm;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_imm_u64(uint64_t u64)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ);
|
|
imm.u64 = u64;
|
|
return imm;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_imm_f(float f)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
|
|
imm.f = f;
|
|
return imm;
|
|
}
|
|
|
|
/** Construct int64_t immediate register */
|
|
static inline struct brw_reg
|
|
brw_imm_q(int64_t q)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_Q);
|
|
imm.d64 = q;
|
|
return imm;
|
|
}
|
|
|
|
/** Construct int64_t immediate register */
|
|
static inline struct brw_reg
|
|
brw_imm_uq(uint64_t uq)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ);
|
|
imm.u64 = uq;
|
|
return imm;
|
|
}
|
|
|
|
/** Construct integer immediate register */
|
|
static inline struct brw_reg
|
|
brw_imm_d(int d)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
|
|
imm.d = d;
|
|
return imm;
|
|
}
|
|
|
|
/** Construct uint immediate register */
|
|
static inline struct brw_reg
|
|
brw_imm_ud(unsigned ud)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
|
|
imm.ud = ud;
|
|
return imm;
|
|
}
|
|
|
|
/** Construct ushort immediate register */
|
|
static inline struct brw_reg
|
|
brw_imm_uw(uint16_t uw)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
|
|
imm.ud = uw | (uw << 16);
|
|
return imm;
|
|
}
|
|
|
|
/** Construct short immediate register */
|
|
static inline struct brw_reg
|
|
brw_imm_w(int16_t w)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
|
|
imm.ud = (uint16_t)w | (uint32_t)(uint16_t)w << 16;
|
|
return imm;
|
|
}
|
|
|
|
/* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
|
|
* numbers alias with _V and _VF below:
|
|
*/
|
|
|
|
/** Construct vector of eight signed half-byte values */
|
|
static inline struct brw_reg
|
|
brw_imm_v(unsigned v)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
|
|
imm.ud = v;
|
|
return imm;
|
|
}
|
|
|
|
/** Construct vector of eight unsigned half-byte values */
|
|
static inline struct brw_reg
|
|
brw_imm_uv(unsigned uv)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UV);
|
|
imm.ud = uv;
|
|
return imm;
|
|
}
|
|
|
|
/** Construct vector of four 8-bit float values */
|
|
static inline struct brw_reg
|
|
brw_imm_vf(unsigned v)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
|
|
imm.ud = v;
|
|
return imm;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_imm_vf4(unsigned v0, unsigned v1, unsigned v2, unsigned v3)
|
|
{
|
|
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
|
|
imm.vstride = BRW_VERTICAL_STRIDE_0;
|
|
imm.width = BRW_WIDTH_4;
|
|
imm.hstride = BRW_HORIZONTAL_STRIDE_1;
|
|
imm.ud = ((v0 << 0) | (v1 << 8) | (v2 << 16) | (v3 << 24));
|
|
return imm;
|
|
}
|
|
|
|
|
|
static inline struct brw_reg
|
|
brw_address(struct brw_reg reg)
|
|
{
|
|
return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
|
|
}
|
|
|
|
/** Construct float[1] general-purpose register */
|
|
static inline struct brw_reg
|
|
brw_vec1_grf(unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
|
|
}
|
|
|
|
/** Construct float[2] general-purpose register */
|
|
static inline struct brw_reg
|
|
brw_vec2_grf(unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
|
|
}
|
|
|
|
/** Construct float[4] general-purpose register */
|
|
static inline struct brw_reg
|
|
brw_vec4_grf(unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
|
|
}
|
|
|
|
/** Construct float[8] general-purpose register */
|
|
static inline struct brw_reg
|
|
brw_vec8_grf(unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
|
|
}
|
|
|
|
/** Construct float[16] general-purpose register */
|
|
static inline struct brw_reg
|
|
brw_vec16_grf(unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_vecn_grf(unsigned width, unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_vecn_reg(width, BRW_GENERAL_REGISTER_FILE, nr, subnr);
|
|
}
|
|
|
|
|
|
static inline struct brw_reg
|
|
brw_uw8_grf(unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_uw16_grf(unsigned nr, unsigned subnr)
|
|
{
|
|
return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
|
|
}
|
|
|
|
|
|
/** Construct null register (usually used for setting condition codes) */
|
|
static inline struct brw_reg
|
|
brw_null_reg(void)
|
|
{
|
|
return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_null_vec(unsigned width)
|
|
{
|
|
return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_address_reg(unsigned subnr)
|
|
{
|
|
return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_tdr_reg(void)
|
|
{
|
|
return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_TDR, 0);
|
|
}
|
|
|
|
/* If/else instructions break in align16 mode if writemask & swizzle
|
|
* aren't xyzw. This goes against the convention for other scalar
|
|
* regs:
|
|
*/
|
|
static inline struct brw_reg
|
|
brw_ip_reg(void)
|
|
{
|
|
return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
|
|
BRW_ARF_IP,
|
|
0,
|
|
0,
|
|
0,
|
|
BRW_REGISTER_TYPE_UD,
|
|
BRW_VERTICAL_STRIDE_4, /* ? */
|
|
BRW_WIDTH_1,
|
|
BRW_HORIZONTAL_STRIDE_0,
|
|
BRW_SWIZZLE_XYZW, /* NOTE! */
|
|
WRITEMASK_XYZW); /* NOTE! */
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_notification_reg(void)
|
|
{
|
|
return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
|
|
BRW_ARF_NOTIFICATION_COUNT,
|
|
0,
|
|
0,
|
|
0,
|
|
BRW_REGISTER_TYPE_UD,
|
|
BRW_VERTICAL_STRIDE_0,
|
|
BRW_WIDTH_1,
|
|
BRW_HORIZONTAL_STRIDE_0,
|
|
BRW_SWIZZLE_XXXX,
|
|
WRITEMASK_X);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_cr0_reg(unsigned subnr)
|
|
{
|
|
return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_CONTROL, subnr);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_sr0_reg(unsigned subnr)
|
|
{
|
|
return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_STATE, subnr);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_acc_reg(unsigned width)
|
|
{
|
|
return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE,
|
|
BRW_ARF_ACCUMULATOR, 0);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_flag_reg(int reg, int subreg)
|
|
{
|
|
return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
|
|
BRW_ARF_FLAG + reg, subreg);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_flag_subreg(unsigned subreg)
|
|
{
|
|
return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
|
|
BRW_ARF_FLAG + subreg / 2, subreg % 2);
|
|
}
|
|
|
|
/**
|
|
* Return the mask register present in Gfx4-5, or the related register present
|
|
* in Gfx7.5 and later hardware referred to as "channel enable" register in
|
|
* the documentation.
|
|
*/
|
|
static inline struct brw_reg
|
|
brw_mask_reg(unsigned subnr)
|
|
{
|
|
return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, subnr);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_vmask_reg()
|
|
{
|
|
return brw_sr0_reg(3);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_dmask_reg()
|
|
{
|
|
return brw_sr0_reg(2);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_mask_stack_reg(unsigned subnr)
|
|
{
|
|
return suboffset(retype(brw_vec16_reg(BRW_ARCHITECTURE_REGISTER_FILE,
|
|
BRW_ARF_MASK_STACK, 0),
|
|
BRW_REGISTER_TYPE_UB), subnr);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_mask_stack_depth_reg(unsigned subnr)
|
|
{
|
|
return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
|
|
BRW_ARF_MASK_STACK_DEPTH, subnr);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_message_reg(unsigned nr)
|
|
{
|
|
return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, nr, 0);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_uvec_mrf(unsigned width, unsigned nr, unsigned subnr)
|
|
{
|
|
return retype(brw_vecn_reg(width, BRW_MESSAGE_REGISTER_FILE, nr, subnr),
|
|
BRW_REGISTER_TYPE_UD);
|
|
}
|
|
|
|
/* This is almost always called with a numeric constant argument, so
|
|
* make things easy to evaluate at compile time:
|
|
*/
|
|
static inline unsigned cvt(unsigned val)
|
|
{
|
|
switch (val) {
|
|
case 0: return 0;
|
|
case 1: return 1;
|
|
case 2: return 2;
|
|
case 4: return 3;
|
|
case 8: return 4;
|
|
case 16: return 5;
|
|
case 32: return 6;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
stride(struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride)
|
|
{
|
|
reg.vstride = cvt(vstride);
|
|
reg.width = cvt(width) - 1;
|
|
reg.hstride = cvt(hstride);
|
|
return reg;
|
|
}
|
|
|
|
/**
|
|
* Multiply the vertical and horizontal stride of a register by the given
|
|
* factor \a s.
|
|
*/
|
|
static inline struct brw_reg
|
|
spread(struct brw_reg reg, unsigned s)
|
|
{
|
|
if (s) {
|
|
assert(util_is_power_of_two_nonzero(s));
|
|
|
|
if (reg.hstride)
|
|
reg.hstride += cvt(s) - 1;
|
|
|
|
if (reg.vstride)
|
|
reg.vstride += cvt(s) - 1;
|
|
|
|
return reg;
|
|
} else {
|
|
return stride(reg, 0, 1, 0);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Reinterpret each channel of register \p reg as a vector of values of the
|
|
* given smaller type and take the i-th subcomponent from each.
|
|
*/
|
|
static inline struct brw_reg
|
|
subscript(struct brw_reg reg, enum brw_reg_type type, unsigned i)
|
|
{
|
|
unsigned scale = type_sz(reg.type) / type_sz(type);
|
|
assert(scale >= 1 && i < scale);
|
|
|
|
if (reg.file == IMM) {
|
|
unsigned bit_size = type_sz(type) * 8;
|
|
reg.u64 >>= i * bit_size;
|
|
reg.u64 &= BITFIELD64_MASK(bit_size);
|
|
if (bit_size <= 16)
|
|
reg.u64 |= reg.u64 << 16;
|
|
return retype(reg, type);
|
|
}
|
|
|
|
return suboffset(retype(spread(reg, scale), type), i);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
vec16(struct brw_reg reg)
|
|
{
|
|
return stride(reg, 16,16,1);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
vec8(struct brw_reg reg)
|
|
{
|
|
return stride(reg, 8,8,1);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
vec4(struct brw_reg reg)
|
|
{
|
|
return stride(reg, 4,4,1);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
vec2(struct brw_reg reg)
|
|
{
|
|
return stride(reg, 2,2,1);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
vec1(struct brw_reg reg)
|
|
{
|
|
return stride(reg, 0,1,0);
|
|
}
|
|
|
|
|
|
static inline struct brw_reg
|
|
get_element(struct brw_reg reg, unsigned elt)
|
|
{
|
|
return vec1(suboffset(reg, elt));
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
get_element_ud(struct brw_reg reg, unsigned elt)
|
|
{
|
|
return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
get_element_d(struct brw_reg reg, unsigned elt)
|
|
{
|
|
return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_D), elt));
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_swizzle(struct brw_reg reg, unsigned swz)
|
|
{
|
|
if (reg.file == BRW_IMMEDIATE_VALUE)
|
|
reg.ud = brw_swizzle_immediate(reg.type, reg.ud, swz);
|
|
else
|
|
reg.swizzle = brw_compose_swizzle(swz, reg.swizzle);
|
|
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_writemask(struct brw_reg reg, unsigned mask)
|
|
{
|
|
assert(reg.file != BRW_IMMEDIATE_VALUE);
|
|
reg.writemask &= mask;
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_set_writemask(struct brw_reg reg, unsigned mask)
|
|
{
|
|
assert(reg.file != BRW_IMMEDIATE_VALUE);
|
|
reg.writemask = mask;
|
|
return reg;
|
|
}
|
|
|
|
static inline unsigned
|
|
brw_writemask_for_size(unsigned n)
|
|
{
|
|
return (1 << n) - 1;
|
|
}
|
|
|
|
static inline unsigned
|
|
brw_writemask_for_component_packing(unsigned n, unsigned first_component)
|
|
{
|
|
assert(first_component + n <= 4);
|
|
return (((1 << n) - 1) << first_component);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
negate(struct brw_reg reg)
|
|
{
|
|
reg.negate ^= 1;
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_abs(struct brw_reg reg)
|
|
{
|
|
reg.abs = 1;
|
|
reg.negate = 0;
|
|
return reg;
|
|
}
|
|
|
|
/************************************************************************/
|
|
|
|
static inline struct brw_reg
|
|
brw_vec4_indirect(unsigned subnr, int offset)
|
|
{
|
|
struct brw_reg reg = brw_vec4_grf(0, 0);
|
|
reg.subnr = subnr;
|
|
reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
|
|
reg.indirect_offset = offset;
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_vec1_indirect(unsigned subnr, int offset)
|
|
{
|
|
struct brw_reg reg = brw_vec1_grf(0, 0);
|
|
reg.subnr = subnr;
|
|
reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
|
|
reg.indirect_offset = offset;
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
brw_VxH_indirect(unsigned subnr, int offset)
|
|
{
|
|
struct brw_reg reg = brw_vec1_grf(0, 0);
|
|
reg.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
|
|
reg.subnr = subnr;
|
|
reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
|
|
reg.indirect_offset = offset;
|
|
return reg;
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
deref_4f(struct brw_indirect ptr, int offset)
|
|
{
|
|
return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
deref_1f(struct brw_indirect ptr, int offset)
|
|
{
|
|
return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
deref_4b(struct brw_indirect ptr, int offset)
|
|
{
|
|
return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
deref_1uw(struct brw_indirect ptr, int offset)
|
|
{
|
|
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
deref_1d(struct brw_indirect ptr, int offset)
|
|
{
|
|
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
deref_1ud(struct brw_indirect ptr, int offset)
|
|
{
|
|
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
|
|
}
|
|
|
|
static inline struct brw_reg
|
|
get_addr_reg(struct brw_indirect ptr)
|
|
{
|
|
return brw_address_reg(ptr.addr_subnr);
|
|
}
|
|
|
|
static inline struct brw_indirect
|
|
brw_indirect_offset(struct brw_indirect ptr, int offset)
|
|
{
|
|
ptr.addr_offset += offset;
|
|
return ptr;
|
|
}
|
|
|
|
static inline struct brw_indirect
|
|
brw_indirect(unsigned addr_subnr, int offset)
|
|
{
|
|
struct brw_indirect ptr;
|
|
ptr.addr_subnr = addr_subnr;
|
|
ptr.addr_offset = offset;
|
|
ptr.pad = 0;
|
|
return ptr;
|
|
}
|
|
|
|
static inline bool
|
|
region_matches(struct brw_reg reg, enum brw_vertical_stride v,
|
|
enum brw_width w, enum brw_horizontal_stride h)
|
|
{
|
|
return reg.vstride == v &&
|
|
reg.width == w &&
|
|
reg.hstride == h;
|
|
}
|
|
|
|
#define has_scalar_region(reg) \
|
|
region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
|
|
BRW_HORIZONTAL_STRIDE_0)
|
|
|
|
/**
|
|
* Return the size in bytes per data element of register \p reg on the
|
|
* corresponding register file.
|
|
*/
|
|
static inline unsigned
|
|
element_sz(struct brw_reg reg)
|
|
{
|
|
if (reg.file == BRW_IMMEDIATE_VALUE || has_scalar_region(reg)) {
|
|
return type_sz(reg.type);
|
|
|
|
} else if (reg.width == BRW_WIDTH_1 &&
|
|
reg.hstride == BRW_HORIZONTAL_STRIDE_0) {
|
|
assert(reg.vstride != BRW_VERTICAL_STRIDE_0);
|
|
return type_sz(reg.type) << (reg.vstride - 1);
|
|
|
|
} else {
|
|
assert(reg.hstride != BRW_HORIZONTAL_STRIDE_0);
|
|
assert(reg.vstride == reg.hstride + reg.width);
|
|
return type_sz(reg.type) << (reg.hstride - 1);
|
|
}
|
|
}
|
|
|
|
/* brw_packed_float.c */
|
|
int brw_float_to_vf(float f);
|
|
float brw_vf_to_float(unsigned char vf);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|