185 lines
6.8 KiB
C
185 lines
6.8 KiB
C
/*
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* Copyright © 2019 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "compiler/nir/nir_builder.h"
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#include "brw_nir.h"
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/**
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* We need to compute alpha to coverage dithering manually in shader
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* and replace sample mask store with the bitwise-AND of sample mask and
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* alpha to coverage dithering.
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*
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* The following formula is used to compute final sample mask:
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* m = int(16.0 * clamp(src0_alpha, 0.0, 1.0))
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* dither_mask = 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) |
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* 0x0808 * (m & 2) | 0x0100 * (m & 1)
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* sample_mask = sample_mask & dither_mask
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*
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* It gives a number of ones proportional to the alpha for 2, 4, 8 or 16
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* least significant bits of the result:
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* 0.0000 0000000000000000
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* 0.0625 0000000100000000
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* 0.1250 0001000000010000
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* 0.1875 0001000100010000
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* 0.2500 1000100010001000
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* 0.3125 1000100110001000
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* 0.3750 1001100010011000
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* 0.4375 1001100110011000
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* 0.5000 1010101010101010
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* 0.5625 1010101110101010
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* 0.6250 1011101010111010
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* 0.6875 1011101110111010
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* 0.7500 1110111011101110
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* 0.8125 1110111111101110
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* 0.8750 1111111011111110
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* 0.9375 1111111111111110
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* 1.0000 1111111111111111
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*/
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static nir_ssa_def *
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build_dither_mask(nir_builder *b, nir_ssa_def *color)
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{
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assert(color->num_components == 4);
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nir_ssa_def *alpha = nir_channel(b, color, 3);
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nir_ssa_def *m =
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nir_f2i32(b, nir_fmul_imm(b, nir_fsat(b, alpha), 16.0));
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nir_ssa_def *part_a =
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nir_iand_imm(b, nir_ushr(b, nir_imm_int(b, 0xfea80),
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nir_iand_imm(b, m, ~3)),
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0xf);
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nir_ssa_def *part_b = nir_iand_imm(b, m, 2);
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nir_ssa_def *part_c = nir_iand_imm(b, m, 1);
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return nir_ior(b, nir_imul_imm(b, part_a, 0x1111),
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nir_ior(b, nir_imul_imm(b, part_b, 0x0808),
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nir_imul_imm(b, part_c, 0x0100)));
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}
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bool
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brw_nir_lower_alpha_to_coverage(nir_shader *shader)
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{
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assert(shader->info.stage == MESA_SHADER_FRAGMENT);
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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const uint64_t outputs_written = shader->info.outputs_written;
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if (!(outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)) ||
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!(outputs_written & (BITFIELD64_BIT(FRAG_RESULT_COLOR) |
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BITFIELD64_BIT(FRAG_RESULT_DATA0))))
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goto skip;
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nir_intrinsic_instr *sample_mask_write = NULL;
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nir_intrinsic_instr *color0_write = NULL;
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bool sample_mask_write_first = false;
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic != nir_intrinsic_store_output)
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continue;
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/* We call nir_lower_io_to_temporaries to lower FS outputs to
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* temporaries with a copy at the end so this should be the last
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* block in the shader.
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*/
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assert(block->cf_node.parent == &impl->cf_node);
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assert(nir_cf_node_is_last(&block->cf_node));
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/* See store_output in fs_visitor::nir_emit_fs_intrinsic */
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const unsigned store_offset = nir_src_as_uint(intrin->src[1]);
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const unsigned driver_location = nir_intrinsic_base(intrin) +
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SET_FIELD(store_offset, BRW_NIR_FRAG_OUTPUT_LOCATION);
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/* Extract the FRAG_RESULT */
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const unsigned location =
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GET_FIELD(driver_location, BRW_NIR_FRAG_OUTPUT_LOCATION);
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if (location == FRAG_RESULT_SAMPLE_MASK) {
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assert(sample_mask_write == NULL);
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sample_mask_write = intrin;
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sample_mask_write_first = (color0_write == NULL);
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}
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if (location == FRAG_RESULT_COLOR ||
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location == FRAG_RESULT_DATA0) {
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assert(color0_write == NULL);
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color0_write = intrin;
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}
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}
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}
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/* It's possible that shader_info may be out-of-date and the writes to
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* either gl_SampleMask or the first color value may have been removed.
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* This can happen if, for instance a nir_ssa_undef is written to the
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* color value. In that case, just bail and don't do anything rather
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* than crashing.
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*/
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if (color0_write == NULL || sample_mask_write == NULL)
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goto skip;
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/* It's possible that the color value isn't actually a vec4. In this case,
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* assuming an alpha of 1.0 and letting the sample mask pass through
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* unaltered seems like the kindest thing to do to apps.
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*/
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assert(color0_write->src[0].is_ssa);
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nir_ssa_def *color0 = color0_write->src[0].ssa;
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if (color0->num_components < 4)
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goto skip;
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assert(sample_mask_write->src[0].is_ssa);
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nir_ssa_def *sample_mask = sample_mask_write->src[0].ssa;
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if (sample_mask_write_first) {
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/* If the sample mask write comes before the write to color0, we need
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* to move it because it's going to use the value from color0 to
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* compute the sample mask.
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*/
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nir_instr_remove(&sample_mask_write->instr);
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nir_instr_insert(nir_after_instr(&color0_write->instr),
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&sample_mask_write->instr);
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}
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nir_builder b;
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nir_builder_init(&b, impl);
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/* Combine dither_mask and the gl_SampleMask value */
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b.cursor = nir_before_instr(&sample_mask_write->instr);
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nir_ssa_def *dither_mask = build_dither_mask(&b, color0);
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dither_mask = nir_iand(&b, sample_mask, dither_mask);
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nir_instr_rewrite_src(&sample_mask_write->instr,
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&sample_mask_write->src[0],
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nir_src_for_ssa(dither_mask));
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nir_metadata_preserve(impl, nir_metadata_block_index |
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nir_metadata_dominance);
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return true;
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skip:
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nir_metadata_preserve(impl, nir_metadata_all);
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return false;
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}
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