380 lines
12 KiB
C++
380 lines
12 KiB
C++
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include "brw_fs.h"
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#include "brw_fs_live_variables.h"
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using namespace brw;
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#define MAX_INSTRUCTION (1 << 30)
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/** @file brw_fs_live_variables.cpp
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*
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* Support for calculating liveness information about virtual GRFs.
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*
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* This produces a live interval for each whole virtual GRF. We could
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* choose to expose per-component live intervals for VGRFs of size > 1,
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* but we currently do not. It is easier for the consumers of this
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* information to work with whole VGRFs.
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*
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* However, we internally track use/def information at the per-GRF level for
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* greater accuracy. Large VGRFs may be accessed piecemeal over many
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* (possibly non-adjacent) instructions. In this case, examining a single
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* instruction is insufficient to decide whether a whole VGRF is ultimately
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* used or defined. Tracking individual components allows us to easily
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* assemble this information.
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*
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* See Muchnick's Advanced Compiler Design and Implementation, section
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* 14.1 (p444).
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*/
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void
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fs_live_variables::setup_one_read(struct block_data *bd,
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int ip, const fs_reg ®)
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{
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int var = var_from_reg(reg);
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assert(var < num_vars);
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start[var] = MIN2(start[var], ip);
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end[var] = MAX2(end[var], ip);
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/* The use[] bitset marks when the block makes use of a variable (VGRF
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* channel) without having completely defined that variable within the
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* block.
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*/
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if (!BITSET_TEST(bd->def, var))
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BITSET_SET(bd->use, var);
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}
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void
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fs_live_variables::setup_one_write(struct block_data *bd, fs_inst *inst,
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int ip, const fs_reg ®)
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{
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int var = var_from_reg(reg);
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assert(var < num_vars);
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start[var] = MIN2(start[var], ip);
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end[var] = MAX2(end[var], ip);
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/* The def[] bitset marks when an initialization in a block completely
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* screens off previous updates of that variable (VGRF channel).
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*/
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if (inst->dst.file == VGRF) {
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if (!inst->is_partial_write() && !BITSET_TEST(bd->use, var))
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BITSET_SET(bd->def, var);
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BITSET_SET(bd->defout, var);
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}
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}
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/**
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* Sets up the use[] and def[] bitsets.
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*
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* The basic-block-level live variable analysis needs to know which
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* variables get used before they're completely defined, and which
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* variables are completely defined before they're used.
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*
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* These are tracked at the per-component level, rather than whole VGRFs.
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*/
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void
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fs_live_variables::setup_def_use()
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{
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int ip = 0;
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foreach_block (block, cfg) {
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assert(ip == block->start_ip);
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if (block->num > 0)
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assert(cfg->blocks[block->num - 1]->end_ip == ip - 1);
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struct block_data *bd = &block_data[block->num];
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foreach_inst_in_block(fs_inst, inst, block) {
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/* Set use[] for this instruction */
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for (unsigned int i = 0; i < inst->sources; i++) {
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fs_reg reg = inst->src[i];
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if (reg.file != VGRF)
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continue;
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for (unsigned j = 0; j < regs_read(inst, i); j++) {
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setup_one_read(bd, ip, reg);
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reg.offset += REG_SIZE;
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}
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}
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bd->flag_use[0] |= inst->flags_read(devinfo) & ~bd->flag_def[0];
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/* Set def[] for this instruction */
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if (inst->dst.file == VGRF) {
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fs_reg reg = inst->dst;
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for (unsigned j = 0; j < regs_written(inst); j++) {
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setup_one_write(bd, inst, ip, reg);
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reg.offset += REG_SIZE;
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}
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}
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if (!inst->predicate && inst->exec_size >= 8)
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bd->flag_def[0] |= inst->flags_written(devinfo) & ~bd->flag_use[0];
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ip++;
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}
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}
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}
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/**
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* The algorithm incrementally sets bits in liveout and livein,
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* propagating it through control flow. It will eventually terminate
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* because it only ever adds bits, and stops when no bits are added in
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* a pass.
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*/
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void
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fs_live_variables::compute_live_variables()
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{
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bool cont = true;
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while (cont) {
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cont = false;
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foreach_block_reverse (block, cfg) {
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struct block_data *bd = &block_data[block->num];
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/* Update liveout */
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foreach_list_typed(bblock_link, child_link, link, &block->children) {
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struct block_data *child_bd = &block_data[child_link->block->num];
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_liveout = (child_bd->livein[i] &
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~bd->liveout[i]);
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if (new_liveout) {
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bd->liveout[i] |= new_liveout;
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cont = true;
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}
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}
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BITSET_WORD new_liveout = (child_bd->flag_livein[0] &
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~bd->flag_liveout[0]);
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if (new_liveout) {
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bd->flag_liveout[0] |= new_liveout;
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cont = true;
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}
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}
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/* Update livein */
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_livein = (bd->use[i] |
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(bd->liveout[i] &
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~bd->def[i]));
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if (new_livein & ~bd->livein[i]) {
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bd->livein[i] |= new_livein;
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cont = true;
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}
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}
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BITSET_WORD new_livein = (bd->flag_use[0] |
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(bd->flag_liveout[0] &
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~bd->flag_def[0]));
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if (new_livein & ~bd->flag_livein[0]) {
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bd->flag_livein[0] |= new_livein;
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cont = true;
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}
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}
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}
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/* Propagate defin and defout down the CFG to calculate the union of live
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* variables potentially defined along any possible control flow path.
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*/
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do {
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cont = false;
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foreach_block (block, cfg) {
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const struct block_data *bd = &block_data[block->num];
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foreach_list_typed(bblock_link, child_link, link, &block->children) {
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struct block_data *child_bd = &block_data[child_link->block->num];
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for (int i = 0; i < bitset_words; i++) {
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const BITSET_WORD new_def = bd->defout[i] & ~child_bd->defin[i];
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child_bd->defin[i] |= new_def;
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child_bd->defout[i] |= new_def;
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cont |= new_def;
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}
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}
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}
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} while (cont);
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}
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/**
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* Extend the start/end ranges for each variable to account for the
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* new information calculated from control flow.
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*/
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void
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fs_live_variables::compute_start_end()
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{
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foreach_block (block, cfg) {
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struct block_data *bd = &block_data[block->num];
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for (int w = 0; w < bitset_words; w++) {
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BITSET_WORD livedefin = bd->livein[w] & bd->defin[w];
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BITSET_WORD livedefout = bd->liveout[w] & bd->defout[w];
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BITSET_WORD livedefinout = livedefin | livedefout;
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while (livedefinout) {
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unsigned b = u_bit_scan(&livedefinout);
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unsigned i = w * BITSET_WORDBITS + b;
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if (livedefin & (1u << b)) {
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start[i] = MIN2(start[i], block->start_ip);
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end[i] = MAX2(end[i], block->start_ip);
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}
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if (livedefout & (1u << b)) {
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start[i] = MIN2(start[i], block->end_ip);
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end[i] = MAX2(end[i], block->end_ip);
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}
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}
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}
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}
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}
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fs_live_variables::fs_live_variables(const backend_shader *s)
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: devinfo(s->devinfo), cfg(s->cfg)
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{
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mem_ctx = ralloc_context(NULL);
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num_vgrfs = s->alloc.count;
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num_vars = 0;
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var_from_vgrf = rzalloc_array(mem_ctx, int, num_vgrfs);
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for (int i = 0; i < num_vgrfs; i++) {
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var_from_vgrf[i] = num_vars;
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num_vars += s->alloc.sizes[i];
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}
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vgrf_from_var = rzalloc_array(mem_ctx, int, num_vars);
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for (int i = 0; i < num_vgrfs; i++) {
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for (unsigned j = 0; j < s->alloc.sizes[i]; j++) {
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vgrf_from_var[var_from_vgrf[i] + j] = i;
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}
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}
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start = ralloc_array(mem_ctx, int, num_vars);
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end = rzalloc_array(mem_ctx, int, num_vars);
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for (int i = 0; i < num_vars; i++) {
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start[i] = MAX_INSTRUCTION;
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end[i] = -1;
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}
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vgrf_start = ralloc_array(mem_ctx, int, num_vgrfs);
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vgrf_end = ralloc_array(mem_ctx, int, num_vgrfs);
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for (int i = 0; i < num_vgrfs; i++) {
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vgrf_start[i] = MAX_INSTRUCTION;
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vgrf_end[i] = -1;
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}
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block_data = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
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bitset_words = BITSET_WORDS(num_vars);
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for (int i = 0; i < cfg->num_blocks; i++) {
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block_data[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].defin = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].defout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].flag_def[0] = 0;
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block_data[i].flag_use[0] = 0;
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block_data[i].flag_livein[0] = 0;
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block_data[i].flag_liveout[0] = 0;
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}
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setup_def_use();
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compute_live_variables();
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compute_start_end();
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/* Merge the per-component live ranges to whole VGRF live ranges. */
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for (int i = 0; i < num_vars; i++) {
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const unsigned vgrf = vgrf_from_var[i];
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vgrf_start[vgrf] = MIN2(vgrf_start[vgrf], start[i]);
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vgrf_end[vgrf] = MAX2(vgrf_end[vgrf], end[i]);
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}
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}
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fs_live_variables::~fs_live_variables()
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{
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ralloc_free(mem_ctx);
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}
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static bool
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check_register_live_range(const fs_live_variables *live, int ip,
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const fs_reg ®, unsigned n)
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{
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const unsigned var = live->var_from_reg(reg);
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if (var + n > unsigned(live->num_vars) ||
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live->vgrf_start[reg.nr] > ip || live->vgrf_end[reg.nr] < ip)
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return false;
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for (unsigned j = 0; j < n; j++) {
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if (live->start[var + j] > ip || live->end[var + j] < ip)
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return false;
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}
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return true;
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}
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bool
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fs_live_variables::validate(const backend_shader *s) const
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{
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int ip = 0;
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foreach_block_and_inst(block, fs_inst, inst, s->cfg) {
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for (unsigned i = 0; i < inst->sources; i++) {
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if (inst->src[i].file == VGRF &&
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!check_register_live_range(this, ip,
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inst->src[i], regs_read(inst, i)))
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return false;
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}
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if (inst->dst.file == VGRF &&
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!check_register_live_range(this, ip, inst->dst, regs_written(inst)))
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return false;
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ip++;
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}
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return true;
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}
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bool
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fs_live_variables::vars_interfere(int a, int b) const
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{
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return !(end[b] <= start[a] ||
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end[a] <= start[b]);
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}
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bool
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fs_live_variables::vgrfs_interfere(int a, int b) const
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{
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return !(vgrf_end[a] <= vgrf_start[b] ||
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vgrf_end[b] <= vgrf_start[a]);
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}
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