631 lines
18 KiB
C++
631 lines
18 KiB
C++
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/** @file brw_fs_combine_constants.cpp
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*
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* This file contains the opt_combine_constants() pass that runs after the
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* regular optimization loop. It passes over the instruction list and
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* selectively promotes immediate values to registers by emitting a mov(1)
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* instruction.
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*
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* This is useful on Gen 7 particularly, because a few instructions can be
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* coissued (i.e., issued in the same cycle as another thread on the same EU
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* issues an instruction) under some circumstances, one of which is that they
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* cannot use immediate values.
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*/
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#include "brw_fs.h"
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#include "brw_cfg.h"
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#include "util/half_float.h"
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using namespace brw;
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static const bool debug = false;
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/* Returns whether an instruction could co-issue if its immediate source were
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* replaced with a GRF source.
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*/
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static bool
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could_coissue(const struct intel_device_info *devinfo, const fs_inst *inst)
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{
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if (devinfo->ver != 7)
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return false;
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switch (inst->opcode) {
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case BRW_OPCODE_MOV:
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case BRW_OPCODE_CMP:
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case BRW_OPCODE_ADD:
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case BRW_OPCODE_MUL:
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/* Only float instructions can coissue. We don't have a great
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* understanding of whether or not something like float(int(a) + int(b))
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* would be considered float (based on the destination type) or integer
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* (based on the source types), so we take the conservative choice of
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* only promoting when both destination and source are float.
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*/
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return inst->dst.type == BRW_REGISTER_TYPE_F &&
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inst->src[0].type == BRW_REGISTER_TYPE_F;
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default:
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return false;
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}
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}
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/**
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* Returns true for instructions that don't support immediate sources.
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*/
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static bool
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must_promote_imm(const struct intel_device_info *devinfo, const fs_inst *inst)
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{
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switch (inst->opcode) {
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case SHADER_OPCODE_POW:
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return devinfo->ver < 8;
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case BRW_OPCODE_MAD:
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case BRW_OPCODE_ADD3:
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case BRW_OPCODE_LRP:
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return true;
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default:
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return false;
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}
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}
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/** A box for putting fs_regs in a linked list. */
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struct reg_link {
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DECLARE_RALLOC_CXX_OPERATORS(reg_link)
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reg_link(fs_reg *reg) : reg(reg) {}
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struct exec_node link;
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fs_reg *reg;
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};
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static struct exec_node *
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link(void *mem_ctx, fs_reg *reg)
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{
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reg_link *l = new(mem_ctx) reg_link(reg);
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return &l->link;
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}
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/**
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* Information about an immediate value.
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*/
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struct imm {
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/** The common ancestor of all blocks using this immediate value. */
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bblock_t *block;
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/**
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* The instruction generating the immediate value, if all uses are contained
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* within a single basic block. Otherwise, NULL.
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*/
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fs_inst *inst;
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/**
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* A list of fs_regs that refer to this immediate. If we promote it, we'll
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* have to patch these up to refer to the new GRF.
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*/
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exec_list *uses;
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/** The immediate value */
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union {
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char bytes[8];
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double df;
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int64_t d64;
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float f;
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int32_t d;
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int16_t w;
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};
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uint8_t size;
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/** When promoting half-float we need to account for certain restrictions */
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bool is_half_float;
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/**
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* The GRF register and subregister number where we've decided to store the
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* constant value.
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*/
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uint8_t subreg_offset;
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uint16_t nr;
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/** The number of coissuable instructions using this immediate. */
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uint16_t uses_by_coissue;
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/**
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* Whether this constant is used by an instruction that can't handle an
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* immediate source (and already has to be promoted to a GRF).
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*/
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bool must_promote;
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uint16_t first_use_ip;
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uint16_t last_use_ip;
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};
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/** The working set of information about immediates. */
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struct table {
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struct imm *imm;
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int size;
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int len;
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};
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static struct imm *
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find_imm(struct table *table, void *data, uint8_t size)
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{
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for (int i = 0; i < table->len; i++) {
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if (table->imm[i].size == size &&
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!memcmp(table->imm[i].bytes, data, size)) {
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return &table->imm[i];
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}
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}
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return NULL;
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}
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static struct imm *
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new_imm(struct table *table, void *mem_ctx)
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{
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if (table->len == table->size) {
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table->size *= 2;
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table->imm = reralloc(mem_ctx, table->imm, struct imm, table->size);
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}
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return &table->imm[table->len++];
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}
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/**
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* Comparator used for sorting an array of imm structures.
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*
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* We sort by basic block number, then last use IP, then first use IP (least
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* to greatest). This sorting causes immediates live in the same area to be
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* allocated to the same register in the hopes that all values will be dead
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* about the same time and the register can be reused.
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*/
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static int
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compare(const void *_a, const void *_b)
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{
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const struct imm *a = (const struct imm *)_a,
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*b = (const struct imm *)_b;
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int block_diff = a->block->num - b->block->num;
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if (block_diff)
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return block_diff;
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int end_diff = a->last_use_ip - b->last_use_ip;
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if (end_diff)
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return end_diff;
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return a->first_use_ip - b->first_use_ip;
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}
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static bool
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get_constant_value(const struct intel_device_info *devinfo,
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const fs_inst *inst, uint32_t src_idx,
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void *out, brw_reg_type *out_type)
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{
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const bool can_do_source_mods = inst->can_do_source_mods(devinfo);
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const fs_reg *src = &inst->src[src_idx];
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*out_type = src->type;
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switch (*out_type) {
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case BRW_REGISTER_TYPE_DF: {
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double val = !can_do_source_mods ? src->df : fabs(src->df);
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memcpy(out, &val, 8);
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break;
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}
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case BRW_REGISTER_TYPE_F: {
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float val = !can_do_source_mods ? src->f : fabsf(src->f);
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memcpy(out, &val, 4);
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break;
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}
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case BRW_REGISTER_TYPE_HF: {
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uint16_t val = src->d & 0xffffu;
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if (can_do_source_mods)
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val = _mesa_float_to_half(fabsf(_mesa_half_to_float(val)));
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memcpy(out, &val, 2);
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break;
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}
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case BRW_REGISTER_TYPE_Q: {
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int64_t val = !can_do_source_mods ? src->d64 : llabs(src->d64);
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memcpy(out, &val, 8);
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break;
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}
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case BRW_REGISTER_TYPE_UQ:
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memcpy(out, &src->u64, 8);
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break;
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case BRW_REGISTER_TYPE_D: {
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int32_t val = !can_do_source_mods ? src->d : abs(src->d);
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memcpy(out, &val, 4);
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break;
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}
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case BRW_REGISTER_TYPE_UD:
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memcpy(out, &src->ud, 4);
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break;
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case BRW_REGISTER_TYPE_W: {
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int16_t val = src->d & 0xffffu;
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if (can_do_source_mods)
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val = abs(val);
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memcpy(out, &val, 2);
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break;
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}
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case BRW_REGISTER_TYPE_UW:
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memcpy(out, &src->ud, 2);
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break;
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default:
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return false;
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};
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return true;
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}
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static struct brw_reg
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build_imm_reg_for_copy(struct imm *imm)
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{
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switch (imm->size) {
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case 8:
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return brw_imm_d(imm->d64);
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case 4:
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return brw_imm_d(imm->d);
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case 2:
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return brw_imm_w(imm->w);
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default:
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unreachable("not implemented");
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}
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}
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static inline uint32_t
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get_alignment_for_imm(const struct imm *imm)
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{
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if (imm->is_half_float)
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return 4; /* At least MAD seems to require this */
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else
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return imm->size;
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}
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static bool
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needs_negate(const fs_reg *reg, const struct imm *imm)
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{
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switch (reg->type) {
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case BRW_REGISTER_TYPE_DF:
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return signbit(reg->df) != signbit(imm->df);
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case BRW_REGISTER_TYPE_F:
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return signbit(reg->f) != signbit(imm->f);
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case BRW_REGISTER_TYPE_Q:
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return (reg->d64 < 0) != (imm->d64 < 0);
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case BRW_REGISTER_TYPE_D:
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return (reg->d < 0) != (imm->d < 0);
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case BRW_REGISTER_TYPE_HF:
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return (reg->d & 0x8000u) != (imm->w & 0x8000u);
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case BRW_REGISTER_TYPE_W:
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return ((int16_t)reg->d < 0) != (imm->w < 0);
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case BRW_REGISTER_TYPE_UQ:
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case BRW_REGISTER_TYPE_UD:
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case BRW_REGISTER_TYPE_UW:
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return false;
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default:
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unreachable("not implemented");
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};
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}
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static bool
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representable_as_hf(float f, uint16_t *hf)
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{
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union fi u;
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uint16_t h = _mesa_float_to_half(f);
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u.f = _mesa_half_to_float(h);
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if (u.f == f) {
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*hf = h;
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return true;
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}
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return false;
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}
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static bool
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representable_as_w(int d, int16_t *w)
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{
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int res = ((d & 0xffff8000) + 0x8000) & 0xffff7fff;
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if (!res) {
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*w = d;
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return true;
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}
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return false;
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}
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static bool
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representable_as_uw(unsigned ud, uint16_t *uw)
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{
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if (!(ud & 0xffff0000)) {
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*uw = ud;
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return true;
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}
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return false;
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}
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static bool
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supports_src_as_imm(const struct intel_device_info *devinfo, enum opcode op)
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{
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switch (op) {
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case BRW_OPCODE_ADD3:
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return devinfo->verx10 >= 125;
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case BRW_OPCODE_MAD:
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return devinfo->ver == 12 && devinfo->verx10 < 125;
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default:
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return false;
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}
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}
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static bool
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can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst,
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unsigned src_idx)
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{
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bool can_promote = false;
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/* Experiment shows that we can only support src0 as immediate */
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if (src_idx != 0)
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return false;
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if (!supports_src_as_imm(devinfo, inst->opcode))
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return false;
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/* TODO - Fix the codepath below to use a bfloat16 immediate on XeHP,
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* since HF/F mixed mode has been removed from the hardware.
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*/
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switch (inst->src[src_idx].type) {
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case BRW_REGISTER_TYPE_F: {
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uint16_t hf;
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if (representable_as_hf(inst->src[src_idx].f, &hf)) {
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inst->src[src_idx] = retype(brw_imm_uw(hf), BRW_REGISTER_TYPE_HF);
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can_promote = true;
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}
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break;
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}
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case BRW_REGISTER_TYPE_W: {
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int16_t w;
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if (representable_as_w(inst->src[src_idx].d, &w)) {
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inst->src[src_idx] = brw_imm_w(w);
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can_promote = true;
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}
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break;
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}
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case BRW_REGISTER_TYPE_UW: {
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uint16_t uw;
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if (representable_as_uw(inst->src[src_idx].ud, &uw)) {
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inst->src[src_idx] = brw_imm_uw(uw);
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can_promote = true;
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}
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break;
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}
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default:
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break;
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}
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return can_promote;
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}
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bool
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fs_visitor::opt_combine_constants()
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{
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void *const_ctx = ralloc_context(NULL);
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struct table table;
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table.size = 8;
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table.len = 0;
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table.imm = ralloc_array(const_ctx, struct imm, table.size);
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const brw::idom_tree &idom = idom_analysis.require();
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unsigned ip = -1;
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/* Make a pass through all instructions and count the number of times each
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* constant is used by coissueable instructions or instructions that cannot
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* take immediate arguments.
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*/
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foreach_block_and_inst(block, fs_inst, inst, cfg) {
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ip++;
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if (!could_coissue(devinfo, inst) && !must_promote_imm(devinfo, inst))
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continue;
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for (int i = 0; i < inst->sources; i++) {
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if (inst->src[i].file != IMM)
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continue;
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if (can_promote_src_as_imm(devinfo, inst, i))
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continue;
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char data[8];
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brw_reg_type type;
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if (!get_constant_value(devinfo, inst, i, data, &type))
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continue;
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uint8_t size = type_sz(type);
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struct imm *imm = find_imm(&table, data, size);
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if (imm) {
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bblock_t *intersection = idom.intersect(block, imm->block);
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if (intersection != imm->block)
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imm->inst = NULL;
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imm->block = intersection;
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imm->uses->push_tail(link(const_ctx, &inst->src[i]));
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imm->uses_by_coissue += could_coissue(devinfo, inst);
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imm->must_promote = imm->must_promote || must_promote_imm(devinfo, inst);
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imm->last_use_ip = ip;
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if (type == BRW_REGISTER_TYPE_HF)
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imm->is_half_float = true;
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} else {
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imm = new_imm(&table, const_ctx);
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imm->block = block;
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imm->inst = inst;
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imm->uses = new(const_ctx) exec_list();
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imm->uses->push_tail(link(const_ctx, &inst->src[i]));
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memcpy(imm->bytes, data, size);
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imm->size = size;
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imm->is_half_float = type == BRW_REGISTER_TYPE_HF;
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imm->uses_by_coissue = could_coissue(devinfo, inst);
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imm->must_promote = must_promote_imm(devinfo, inst);
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imm->first_use_ip = ip;
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imm->last_use_ip = ip;
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}
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}
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}
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|
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/* Remove constants from the table that don't have enough uses to make them
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* profitable to store in a register.
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*/
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for (int i = 0; i < table.len;) {
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struct imm *imm = &table.imm[i];
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if (!imm->must_promote && imm->uses_by_coissue < 4) {
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table.imm[i] = table.imm[table.len - 1];
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table.len--;
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continue;
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}
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i++;
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}
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if (table.len == 0) {
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ralloc_free(const_ctx);
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return false;
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}
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if (cfg->num_blocks != 1)
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qsort(table.imm, table.len, sizeof(struct imm), compare);
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|
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/* Insert MOVs to load the constant values into GRFs. */
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fs_reg reg(VGRF, alloc.allocate(1));
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reg.stride = 0;
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for (int i = 0; i < table.len; i++) {
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struct imm *imm = &table.imm[i];
|
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/* Insert it either before the instruction that generated the immediate
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* or after the last non-control flow instruction of the common ancestor.
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*/
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exec_node *n = (imm->inst ? imm->inst :
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imm->block->last_non_control_flow_inst()->next);
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|
|
/* From the BDW and CHV PRM, 3D Media GPGPU, Special Restrictions:
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|
*
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|
* "In Align16 mode, the channel selects and channel enables apply to a
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|
* pair of half-floats, because these parameters are defined for DWord
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* elements ONLY. This is applicable when both source and destination
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* are half-floats."
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|
*
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* This means that Align16 instructions that use promoted HF immediates
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|
* and use a <0,1,0>:HF region would read 2 HF slots instead of
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|
* replicating the single one we want. To avoid this, we always populate
|
|
* both HF slots within a DWord with the constant.
|
|
*/
|
|
const uint32_t width = devinfo->ver == 8 && imm->is_half_float ? 2 : 1;
|
|
const fs_builder ibld = bld.at(imm->block, n).exec_all().group(width, 0);
|
|
|
|
/* Put the immediate in an offset aligned to its size. Some instructions
|
|
* seem to have additional alignment requirements, so account for that
|
|
* too.
|
|
*/
|
|
reg.offset = ALIGN(reg.offset, get_alignment_for_imm(imm));
|
|
|
|
/* Ensure we have enough space in the register to copy the immediate */
|
|
struct brw_reg imm_reg = build_imm_reg_for_copy(imm);
|
|
if (reg.offset + type_sz(imm_reg.type) * width > REG_SIZE) {
|
|
reg.nr = alloc.allocate(1);
|
|
reg.offset = 0;
|
|
}
|
|
|
|
ibld.MOV(retype(reg, imm_reg.type), imm_reg);
|
|
imm->nr = reg.nr;
|
|
imm->subreg_offset = reg.offset;
|
|
|
|
reg.offset += imm->size * width;
|
|
}
|
|
shader_stats.promoted_constants = table.len;
|
|
|
|
/* Rewrite the immediate sources to refer to the new GRFs. */
|
|
for (int i = 0; i < table.len; i++) {
|
|
foreach_list_typed(reg_link, link, link, table.imm[i].uses) {
|
|
fs_reg *reg = link->reg;
|
|
#ifdef DEBUG
|
|
switch (reg->type) {
|
|
case BRW_REGISTER_TYPE_DF:
|
|
assert((isnan(reg->df) && isnan(table.imm[i].df)) ||
|
|
(fabs(reg->df) == fabs(table.imm[i].df)));
|
|
break;
|
|
case BRW_REGISTER_TYPE_F:
|
|
assert((isnan(reg->f) && isnan(table.imm[i].f)) ||
|
|
(fabsf(reg->f) == fabsf(table.imm[i].f)));
|
|
break;
|
|
case BRW_REGISTER_TYPE_HF:
|
|
assert((isnan(_mesa_half_to_float(reg->d & 0xffffu)) &&
|
|
isnan(_mesa_half_to_float(table.imm[i].w))) ||
|
|
(fabsf(_mesa_half_to_float(reg->d & 0xffffu)) ==
|
|
fabsf(_mesa_half_to_float(table.imm[i].w))));
|
|
break;
|
|
case BRW_REGISTER_TYPE_Q:
|
|
assert(abs(reg->d64) == abs(table.imm[i].d64));
|
|
break;
|
|
case BRW_REGISTER_TYPE_UQ:
|
|
assert(reg->d64 == table.imm[i].d64);
|
|
break;
|
|
case BRW_REGISTER_TYPE_D:
|
|
assert(abs(reg->d) == abs(table.imm[i].d));
|
|
break;
|
|
case BRW_REGISTER_TYPE_UD:
|
|
assert(reg->d == table.imm[i].d);
|
|
break;
|
|
case BRW_REGISTER_TYPE_W:
|
|
assert(abs((int16_t) (reg->d & 0xffff)) == table.imm[i].w);
|
|
break;
|
|
case BRW_REGISTER_TYPE_UW:
|
|
assert((reg->ud & 0xffffu) == (uint16_t) table.imm[i].w);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
reg->file = VGRF;
|
|
reg->offset = table.imm[i].subreg_offset;
|
|
reg->stride = 0;
|
|
reg->negate = needs_negate(reg, &table.imm[i]);
|
|
reg->nr = table.imm[i].nr;
|
|
}
|
|
}
|
|
|
|
if (debug) {
|
|
for (int i = 0; i < table.len; i++) {
|
|
struct imm *imm = &table.imm[i];
|
|
|
|
printf("0x%016" PRIx64 " - block %3d, reg %3d sub %2d, "
|
|
"Uses: (%2d, %2d), IP: %4d to %4d, length %4d\n",
|
|
(uint64_t)(imm->d & BITFIELD64_MASK(imm->size * 8)),
|
|
imm->block->num,
|
|
imm->nr,
|
|
imm->subreg_offset,
|
|
imm->must_promote,
|
|
imm->uses_by_coissue,
|
|
imm->first_use_ip,
|
|
imm->last_use_ip,
|
|
imm->last_use_ip - imm->first_use_ip);
|
|
}
|
|
}
|
|
|
|
ralloc_free(const_ctx);
|
|
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
|
|
|
|
return true;
|
|
}
|