668 lines
25 KiB
C++
668 lines
25 KiB
C++
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifndef BRW_FS_H
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#define BRW_FS_H
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#include "brw_shader.h"
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#include "brw_ir_fs.h"
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#include "brw_fs_builder.h"
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#include "brw_fs_live_variables.h"
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#include "brw_ir_performance.h"
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#include "compiler/nir/nir.h"
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struct bblock_t;
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namespace {
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struct acp_entry;
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}
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class fs_visitor;
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namespace brw {
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/**
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* Register pressure analysis of a shader. Estimates how many registers
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* are live at any point of the program in GRF units.
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*/
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struct register_pressure {
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register_pressure(const fs_visitor *v);
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~register_pressure();
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analysis_dependency_class
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dependency_class() const
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{
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return (DEPENDENCY_INSTRUCTION_IDENTITY |
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DEPENDENCY_INSTRUCTION_DATA_FLOW |
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DEPENDENCY_VARIABLES);
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}
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bool
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validate(const fs_visitor *) const
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{
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/* FINISHME */
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return true;
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}
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unsigned *regs_live_at_ip;
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};
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}
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struct brw_gs_compile;
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static inline fs_reg
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offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta)
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{
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return offset(reg, bld.dispatch_width(), delta);
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}
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struct shader_stats {
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const char *scheduler_mode;
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unsigned promoted_constants;
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unsigned spill_count;
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unsigned fill_count;
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};
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/**
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* The fragment shader front-end.
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*
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* Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
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*/
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class fs_visitor : public backend_shader
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{
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public:
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fs_visitor(const struct brw_compiler *compiler, void *log_data,
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void *mem_ctx,
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const brw_base_prog_key *key,
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struct brw_stage_prog_data *prog_data,
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const nir_shader *shader,
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unsigned dispatch_width,
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bool debug_enabled);
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fs_visitor(const struct brw_compiler *compiler, void *log_data,
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void *mem_ctx,
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struct brw_gs_compile *gs_compile,
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struct brw_gs_prog_data *prog_data,
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const nir_shader *shader,
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bool debug_enabled);
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void init();
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~fs_visitor();
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fs_reg vgrf(const glsl_type *const type);
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void import_uniforms(fs_visitor *v);
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void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
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const fs_reg &dst,
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const fs_reg &surf_index,
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const fs_reg &varying_offset,
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uint32_t const_offset,
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uint8_t alignment);
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void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
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bool run_fs(bool allow_spilling, bool do_rep_send);
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bool run_vs();
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bool run_tcs();
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bool run_tes();
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bool run_gs();
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bool run_cs(bool allow_spilling);
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bool run_bs(bool allow_spilling);
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bool run_task(bool allow_spilling);
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bool run_mesh(bool allow_spilling);
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void optimize();
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void allocate_registers(bool allow_spilling);
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void setup_fs_payload_gfx4();
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void setup_fs_payload_gfx6();
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void setup_vs_payload();
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void setup_gs_payload();
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void setup_cs_payload();
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bool fixup_sends_duplicate_payload();
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void fixup_3src_null_dest();
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void emit_dummy_memory_fence_before_eot();
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bool fixup_nomask_control_flow();
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void assign_curb_setup();
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void assign_urb_setup();
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void convert_attr_sources_to_hw_regs(fs_inst *inst);
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void assign_vs_urb_setup();
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void assign_tcs_urb_setup();
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void assign_tes_urb_setup();
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void assign_gs_urb_setup();
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bool assign_regs(bool allow_spilling, bool spill_all);
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void assign_regs_trivial();
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void calculate_payload_ranges(int payload_node_count,
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int *payload_last_use_ip) const;
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bool split_virtual_grfs();
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bool compact_virtual_grfs();
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void assign_constant_locations();
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bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index,
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unsigned *out_pull_index);
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void lower_constant_loads();
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virtual void invalidate_analysis(brw::analysis_dependency_class c);
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void validate();
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bool opt_algebraic();
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bool opt_redundant_halt();
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bool opt_cse();
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bool opt_cse_local(const brw::fs_live_variables &live, bblock_t *block, int &ip);
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bool opt_copy_propagation();
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bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
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bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
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bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block,
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exec_list *acp);
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bool opt_drop_redundant_mov_to_flags();
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bool opt_register_renaming();
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bool opt_bank_conflicts();
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bool opt_split_sends();
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bool register_coalesce();
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bool compute_to_mrf();
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bool eliminate_find_live_channel();
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bool dead_code_eliminate();
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bool remove_duplicate_mrf_writes();
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bool remove_extra_rounding_modes();
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void schedule_instructions(instruction_scheduler_mode mode);
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void insert_gfx4_send_dependency_workarounds();
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void insert_gfx4_pre_send_dependency_workarounds(bblock_t *block,
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fs_inst *inst);
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void insert_gfx4_post_send_dependency_workarounds(bblock_t *block,
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fs_inst *inst);
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void vfail(const char *msg, va_list args);
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void fail(const char *msg, ...);
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void limit_dispatch_width(unsigned n, const char *msg);
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void lower_uniform_pull_constant_loads();
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bool lower_load_payload();
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bool lower_pack();
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bool lower_regioning();
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bool lower_logical_sends();
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bool lower_integer_multiplication();
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bool lower_minmax();
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bool lower_simd_width();
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bool lower_barycentrics();
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bool lower_derivatives();
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bool lower_scoreboard();
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bool lower_sub_sat();
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bool opt_combine_constants();
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void emit_dummy_fs();
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void emit_repclear_shader();
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void emit_fragcoord_interpolation(fs_reg wpos);
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void emit_is_helper_invocation(fs_reg result);
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fs_reg emit_frontfacing_interpolation();
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fs_reg emit_samplepos_setup();
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fs_reg emit_sampleid_setup();
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fs_reg emit_samplemaskin_setup();
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fs_reg emit_shading_rate_setup();
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void emit_interpolation_setup_gfx4();
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void emit_interpolation_setup_gfx6();
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fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
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const fs_reg &texture,
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const fs_reg &texture_handle);
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fs_reg resolve_source_modifiers(const fs_reg &src);
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void emit_fsign(const class brw::fs_builder &, const nir_alu_instr *instr,
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fs_reg result, fs_reg *op, unsigned fsign_src);
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void emit_shader_float_controls_execution_mode();
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bool opt_peephole_sel();
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bool opt_peephole_predicated_break();
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bool opt_saturate_propagation();
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bool opt_cmod_propagation();
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bool opt_zero_samples();
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void set_tcs_invocation_id();
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void emit_nir_code();
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void nir_setup_outputs();
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void nir_setup_uniforms();
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void nir_emit_system_values();
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void nir_emit_impl(nir_function_impl *impl);
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void nir_emit_cf_list(exec_list *list);
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void nir_emit_if(nir_if *if_stmt);
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void nir_emit_loop(nir_loop *loop);
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void nir_emit_block(nir_block *block);
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void nir_emit_instr(nir_instr *instr);
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void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr,
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bool need_dest);
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bool try_emit_b2fi_of_inot(const brw::fs_builder &bld, fs_reg result,
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nir_alu_instr *instr);
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void nir_emit_load_const(const brw::fs_builder &bld,
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nir_load_const_instr *instr);
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void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_bs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_task_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_mesh_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_task_mesh_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg swizzle_nir_scratch_addr(const brw::fs_builder &bld,
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const fs_reg &addr,
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bool in_dwords);
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void nir_emit_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_ssbo_atomic_float(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_shared_atomic(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_shared_atomic_float(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_global_atomic(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_global_atomic_float(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_texture(const brw::fs_builder &bld,
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nir_tex_instr *instr);
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void nir_emit_jump(const brw::fs_builder &bld,
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nir_jump_instr *instr);
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fs_reg get_nir_src(const nir_src &src);
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fs_reg get_nir_src_imm(const nir_src &src);
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fs_reg get_nir_dest(const nir_dest &dest);
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fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
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fs_reg get_tcs_single_patch_icp_handle(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg get_tcs_eight_patch_icp_handle(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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struct brw_reg get_tcs_output_urb_handle();
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void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
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unsigned wr_mask);
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bool optimize_extract_to_float(nir_alu_instr *instr,
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const fs_reg &result);
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bool optimize_frontfacing_ternary(nir_alu_instr *instr,
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const fs_reg &result);
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void emit_alpha_test();
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fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
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fs_reg color1, fs_reg color2,
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fs_reg src0_alpha, unsigned components);
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void emit_fb_writes();
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fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
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const fs_reg &dst, unsigned target);
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void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
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void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
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unsigned stream_id);
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void emit_gs_control_data_bits(const fs_reg &vertex_count);
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void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
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void emit_gs_vertex(const nir_src &vertex_count_nir_src,
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unsigned stream_id);
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void emit_gs_thread_end();
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void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
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unsigned base_offset, const nir_src &offset_src,
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unsigned num_components, unsigned first_component);
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void emit_cs_terminate();
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fs_reg emit_work_group_id_setup();
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void emit_task_mesh_store(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void emit_task_mesh_load(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void emit_barrier();
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fs_reg get_timestamp(const brw::fs_builder &bld);
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fs_reg interp_reg(int location, int channel);
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fs_reg per_primitive_reg(int location);
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virtual void dump_instructions() const;
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virtual void dump_instructions(const char *name) const;
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void dump_instruction(const backend_instruction *inst) const;
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void dump_instruction(const backend_instruction *inst, FILE *file) const;
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const brw_base_prog_key *const key;
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const struct brw_sampler_prog_key_data *key_tex;
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struct brw_gs_compile *gs_compile;
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struct brw_stage_prog_data *prog_data;
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brw_analysis<brw::fs_live_variables, backend_shader> live_analysis;
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brw_analysis<brw::register_pressure, fs_visitor> regpressure_analysis;
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brw_analysis<brw::performance, fs_visitor> performance_analysis;
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/** Number of uniform variable components visited. */
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unsigned uniforms;
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/** Byte-offset for the next available spot in the scratch space buffer. */
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unsigned last_scratch;
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/**
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* Array mapping UNIFORM register numbers to the push parameter index,
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* or -1 if this uniform register isn't being uploaded as a push constant.
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*/
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int *push_constant_loc;
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fs_reg subgroup_id;
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fs_reg group_size[3];
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fs_reg scratch_base;
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fs_reg frag_depth;
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fs_reg frag_stencil;
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fs_reg sample_mask;
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fs_reg outputs[VARYING_SLOT_MAX];
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fs_reg dual_src_output;
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int first_non_payload_grf;
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/** Either BRW_MAX_GRF or GFX7_MRF_HACK_START */
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unsigned max_grf;
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fs_reg *nir_locals;
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fs_reg *nir_ssa_values;
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fs_reg *nir_system_values;
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bool failed;
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char *fail_msg;
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/** Register numbers for thread payload fields. */
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struct thread_payload {
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uint8_t subspan_coord_reg[2];
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uint8_t source_depth_reg[2];
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uint8_t source_w_reg[2];
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uint8_t aa_dest_stencil_reg[2];
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uint8_t dest_depth_reg[2];
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uint8_t sample_pos_reg[2];
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uint8_t sample_mask_in_reg[2];
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uint8_t depth_w_coef_reg[2];
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uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2];
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uint8_t local_invocation_id_reg[2];
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/** The number of thread payload registers the hardware will supply. */
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uint8_t num_regs;
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} payload;
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bool source_depth_to_render_target;
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bool runtime_check_aads_emit;
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fs_reg pixel_x;
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fs_reg pixel_y;
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fs_reg pixel_z;
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fs_reg wpos_w;
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fs_reg pixel_w;
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fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
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fs_reg shader_start_time;
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fs_reg final_gs_vertex_count;
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fs_reg control_data_bits;
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fs_reg invocation_id;
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unsigned grf_used;
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bool spilled_any_registers;
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const unsigned dispatch_width; /**< 8, 16 or 32 */
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unsigned max_dispatch_width;
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struct shader_stats shader_stats;
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brw::fs_builder bld;
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private:
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fs_reg prepare_alu_destination_and_sources(const brw::fs_builder &bld,
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nir_alu_instr *instr,
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fs_reg *op,
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bool need_dest);
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void resolve_inot_sources(const brw::fs_builder &bld, nir_alu_instr *instr,
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fs_reg *op);
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void lower_mul_dword_inst(fs_inst *inst, bblock_t *block);
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void lower_mul_qword_inst(fs_inst *inst, bblock_t *block);
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void lower_mulh_inst(fs_inst *inst, bblock_t *block);
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unsigned workgroup_size() const;
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};
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/**
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* Return the flag register used in fragment shaders to keep track of live
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* samples. On Gfx7+ we use f1.0-f1.1 to allow discard jumps in SIMD32
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* dispatch mode, while earlier generations are constrained to f0.1, which
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* limits the dispatch width to SIMD16 for fragment shaders that use discard.
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|
*/
|
|
static inline unsigned
|
|
sample_mask_flag_subreg(const fs_visitor *shader)
|
|
{
|
|
assert(shader->stage == MESA_SHADER_FRAGMENT);
|
|
return shader->devinfo->ver >= 7 ? 2 : 1;
|
|
}
|
|
|
|
/**
|
|
* The fragment shader code generator.
|
|
*
|
|
* Translates FS IR to actual i965 assembly code.
|
|
*/
|
|
class fs_generator
|
|
{
|
|
public:
|
|
fs_generator(const struct brw_compiler *compiler, void *log_data,
|
|
void *mem_ctx,
|
|
struct brw_stage_prog_data *prog_data,
|
|
bool runtime_check_aads_emit,
|
|
gl_shader_stage stage);
|
|
~fs_generator();
|
|
|
|
void enable_debug(const char *shader_name);
|
|
int generate_code(const cfg_t *cfg, int dispatch_width,
|
|
struct shader_stats shader_stats,
|
|
const brw::performance &perf,
|
|
struct brw_compile_stats *stats);
|
|
void add_const_data(void *data, unsigned size);
|
|
void add_resume_sbt(unsigned num_resume_shaders, uint64_t *sbt);
|
|
const unsigned *get_assembly();
|
|
|
|
private:
|
|
void fire_fb_write(fs_inst *inst,
|
|
struct brw_reg payload,
|
|
struct brw_reg implied_header,
|
|
GLuint nr);
|
|
void generate_send(fs_inst *inst,
|
|
struct brw_reg dst,
|
|
struct brw_reg desc,
|
|
struct brw_reg ex_desc,
|
|
struct brw_reg payload,
|
|
struct brw_reg payload2);
|
|
void generate_fb_write(fs_inst *inst, struct brw_reg payload);
|
|
void generate_fb_read(fs_inst *inst, struct brw_reg dst,
|
|
struct brw_reg payload);
|
|
void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
|
|
void generate_urb_write(fs_inst *inst, struct brw_reg payload);
|
|
void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
|
|
void generate_barrier(fs_inst *inst, struct brw_reg src);
|
|
bool generate_linterp(fs_inst *inst, struct brw_reg dst,
|
|
struct brw_reg *src);
|
|
void generate_tex(fs_inst *inst, struct brw_reg dst,
|
|
struct brw_reg surface_index,
|
|
struct brw_reg sampler_index);
|
|
void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
|
|
struct brw_reg src,
|
|
struct brw_reg surf_index);
|
|
void generate_ddx(const fs_inst *inst,
|
|
struct brw_reg dst, struct brw_reg src);
|
|
void generate_ddy(const fs_inst *inst,
|
|
struct brw_reg dst, struct brw_reg src);
|
|
void generate_scratch_write(fs_inst *inst, struct brw_reg src);
|
|
void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
|
|
void generate_scratch_read_gfx7(fs_inst *inst, struct brw_reg dst);
|
|
void generate_scratch_header(fs_inst *inst, struct brw_reg dst);
|
|
void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
|
|
struct brw_reg index,
|
|
struct brw_reg offset);
|
|
void generate_uniform_pull_constant_load_gfx7(fs_inst *inst,
|
|
struct brw_reg dst,
|
|
struct brw_reg surf_index,
|
|
struct brw_reg payload);
|
|
void generate_varying_pull_constant_load_gfx4(fs_inst *inst,
|
|
struct brw_reg dst,
|
|
struct brw_reg index);
|
|
void generate_mov_dispatch_to_flags(fs_inst *inst);
|
|
|
|
void generate_pixel_interpolator_query(fs_inst *inst,
|
|
struct brw_reg dst,
|
|
struct brw_reg src,
|
|
struct brw_reg msg_data,
|
|
unsigned msg_type);
|
|
|
|
void generate_set_sample_id(fs_inst *inst,
|
|
struct brw_reg dst,
|
|
struct brw_reg src0,
|
|
struct brw_reg src1);
|
|
|
|
void generate_halt(fs_inst *inst);
|
|
|
|
void generate_pack_half_2x16_split(fs_inst *inst,
|
|
struct brw_reg dst,
|
|
struct brw_reg x,
|
|
struct brw_reg y);
|
|
|
|
void generate_mov_indirect(fs_inst *inst,
|
|
struct brw_reg dst,
|
|
struct brw_reg reg,
|
|
struct brw_reg indirect_byte_offset);
|
|
|
|
void generate_shuffle(fs_inst *inst,
|
|
struct brw_reg dst,
|
|
struct brw_reg src,
|
|
struct brw_reg idx);
|
|
|
|
void generate_quad_swizzle(const fs_inst *inst,
|
|
struct brw_reg dst, struct brw_reg src,
|
|
unsigned swiz);
|
|
|
|
bool patch_halt_jumps();
|
|
|
|
const struct brw_compiler *compiler;
|
|
void *log_data; /* Passed to compiler->*_log functions */
|
|
|
|
const struct intel_device_info *devinfo;
|
|
|
|
struct brw_codegen *p;
|
|
struct brw_stage_prog_data * const prog_data;
|
|
|
|
unsigned dispatch_width; /**< 8, 16 or 32 */
|
|
|
|
exec_list discard_halt_patches;
|
|
bool runtime_check_aads_emit;
|
|
bool debug_flag;
|
|
const char *shader_name;
|
|
gl_shader_stage stage;
|
|
void *mem_ctx;
|
|
};
|
|
|
|
namespace brw {
|
|
inline fs_reg
|
|
fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2],
|
|
brw_reg_type type = BRW_REGISTER_TYPE_F)
|
|
{
|
|
if (!regs[0])
|
|
return fs_reg();
|
|
|
|
if (bld.dispatch_width() > 16) {
|
|
const fs_reg tmp = bld.vgrf(type);
|
|
const brw::fs_builder hbld = bld.exec_all().group(16, 0);
|
|
const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
|
|
fs_reg components[2];
|
|
assert(m <= 2);
|
|
|
|
for (unsigned g = 0; g < m; g++)
|
|
components[g] = retype(brw_vec8_grf(regs[g], 0), type);
|
|
|
|
hbld.LOAD_PAYLOAD(tmp, components, m, 0);
|
|
|
|
return tmp;
|
|
|
|
} else {
|
|
return fs_reg(retype(brw_vec8_grf(regs[0], 0), type));
|
|
}
|
|
}
|
|
|
|
inline fs_reg
|
|
fetch_barycentric_reg(const brw::fs_builder &bld, uint8_t regs[2])
|
|
{
|
|
if (!regs[0])
|
|
return fs_reg();
|
|
|
|
const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
|
|
const brw::fs_builder hbld = bld.exec_all().group(8, 0);
|
|
const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
|
|
fs_reg *const components = new fs_reg[2 * m];
|
|
|
|
for (unsigned c = 0; c < 2; c++) {
|
|
for (unsigned g = 0; g < m; g++)
|
|
components[c * m + g] = offset(brw_vec8_grf(regs[g / 2], 0),
|
|
hbld, c + 2 * (g % 2));
|
|
}
|
|
|
|
hbld.LOAD_PAYLOAD(tmp, components, 2 * m, 0);
|
|
|
|
delete[] components;
|
|
return tmp;
|
|
}
|
|
|
|
bool
|
|
lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i);
|
|
}
|
|
|
|
void shuffle_from_32bit_read(const brw::fs_builder &bld,
|
|
const fs_reg &dst,
|
|
const fs_reg &src,
|
|
uint32_t first_component,
|
|
uint32_t components);
|
|
|
|
fs_reg setup_imm_df(const brw::fs_builder &bld,
|
|
double v);
|
|
|
|
fs_reg setup_imm_b(const brw::fs_builder &bld,
|
|
int8_t v);
|
|
|
|
fs_reg setup_imm_ub(const brw::fs_builder &bld,
|
|
uint8_t v);
|
|
|
|
enum brw_barycentric_mode brw_barycentric_mode(nir_intrinsic_instr *intr);
|
|
|
|
uint32_t brw_fb_write_msg_control(const fs_inst *inst,
|
|
const struct brw_wm_prog_data *prog_data);
|
|
|
|
void brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data);
|
|
|
|
void brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width);
|
|
|
|
namespace brw {
|
|
class fs_builder;
|
|
}
|
|
|
|
fs_reg brw_sample_mask_reg(const brw::fs_builder &bld);
|
|
void brw_emit_predicate_on_sample_mask(const brw::fs_builder &bld, fs_inst *inst);
|
|
|
|
#endif /* BRW_FS_H */
|