113 lines
3.7 KiB
C
113 lines
3.7 KiB
C
/*
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* Copyright © 2011 Red Hat All Rights Reserved.
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* Copyright © 2014 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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#include "amdgpu_winsys.h"
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#include "util/format/u_format.h"
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static int amdgpu_surface_sanity(const struct pipe_resource *tex)
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{
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switch (tex->target) {
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case PIPE_TEXTURE_1D:
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if (tex->height0 > 1)
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return -EINVAL;
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FALLTHROUGH;
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case PIPE_TEXTURE_2D:
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case PIPE_TEXTURE_RECT:
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if (tex->depth0 > 1 || tex->array_size > 1)
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return -EINVAL;
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break;
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case PIPE_TEXTURE_3D:
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if (tex->array_size > 1)
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return -EINVAL;
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break;
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case PIPE_TEXTURE_1D_ARRAY:
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if (tex->height0 > 1)
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return -EINVAL;
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FALLTHROUGH;
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case PIPE_TEXTURE_CUBE:
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case PIPE_TEXTURE_2D_ARRAY:
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case PIPE_TEXTURE_CUBE_ARRAY:
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if (tex->depth0 > 1)
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return -EINVAL;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int amdgpu_surface_init(struct radeon_winsys *rws,
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const struct pipe_resource *tex,
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uint64_t flags, unsigned bpe,
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enum radeon_surf_mode mode,
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struct radeon_surf *surf)
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{
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struct amdgpu_winsys *ws = amdgpu_winsys(rws);
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int r;
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r = amdgpu_surface_sanity(tex);
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if (r)
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return r;
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surf->blk_w = util_format_get_blockwidth(tex->format);
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surf->blk_h = util_format_get_blockheight(tex->format);
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surf->bpe = bpe;
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surf->flags = flags;
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struct ac_surf_config config;
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config.info.width = tex->width0;
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config.info.height = tex->height0;
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config.info.depth = tex->depth0;
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config.info.array_size = tex->array_size;
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config.info.samples = tex->nr_samples;
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config.info.storage_samples = tex->nr_storage_samples;
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config.info.levels = tex->last_level + 1;
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config.info.num_channels = util_format_get_nr_components(tex->format);
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config.is_1d = tex->target == PIPE_TEXTURE_1D ||
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tex->target == PIPE_TEXTURE_1D_ARRAY;
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config.is_3d = tex->target == PIPE_TEXTURE_3D;
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config.is_cube = tex->target == PIPE_TEXTURE_CUBE;
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/* Use different surface counters for color and FMASK, so that MSAA MRTs
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* always use consecutive surface indices when FMASK is allocated between
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* them.
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*/
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config.info.surf_index = &ws->surf_index_color;
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config.info.fmask_surf_index = &ws->surf_index_fmask;
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if (flags & RADEON_SURF_Z_OR_SBUFFER)
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config.info.surf_index = NULL;
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return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
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}
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void amdgpu_surface_init_functions(struct amdgpu_screen_winsys *ws)
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{
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ws->base.surface_init = amdgpu_surface_init;
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}
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