207 lines
6.9 KiB
C
207 lines
6.9 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Marek Olšák <maraeo@gmail.com>
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*/
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/**
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* This file contains helpers for writing commands to commands streams.
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*/
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#ifndef R600_CS_H
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#define R600_CS_H
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#include "r600_pipe_common.h"
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#include "r600d_common.h"
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/**
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* Return true if there is enough memory in VRAM and GTT for the buffers
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* added so far.
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*
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* \param vram VRAM memory size not added to the buffer list yet
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* \param gtt GTT memory size not added to the buffer list yet
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*/
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static inline bool
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radeon_cs_memory_below_limit(struct r600_common_screen *screen,
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struct radeon_cmdbuf *cs,
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uint64_t vram, uint64_t gtt)
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{
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vram += (uint64_t)cs->used_vram_kb * 1024;
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gtt += (uint64_t)cs->used_gart_kb * 1024;
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/* Anything that goes above the VRAM size should go to GTT. */
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if (vram > (uint64_t)screen->info.vram_size_kb * 1024)
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gtt += vram - (uint64_t)screen->info.vram_size_kb * 1024;
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/* Now we just need to check if we have enough GTT. */
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return gtt < (uint64_t)screen->info.gart_size_kb * 1024 * 0.7;
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}
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/**
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* Add a buffer to the buffer list for the given command stream (CS).
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*
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* All buffers used by a CS must be added to the list. This tells the kernel
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* driver which buffers are used by GPU commands. Other buffers can
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* be swapped out (not accessible) during execution.
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*
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* The buffer list becomes empty after every context flush and must be
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* rebuilt.
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*/
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static inline unsigned radeon_add_to_buffer_list(struct r600_common_context *rctx,
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struct r600_ring *ring,
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struct r600_resource *rbo,
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unsigned usage)
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{
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assert(usage);
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return rctx->ws->cs_add_buffer(
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&ring->cs, rbo->buf,
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usage | RADEON_USAGE_SYNCHRONIZED,
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rbo->domains) * 4;
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}
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/**
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* Same as above, but also checks memory usage and flushes the context
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* accordingly.
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*
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* When this SHOULD NOT be used:
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*
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* - if r600_context_add_resource_size has been called for the buffer
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* followed by *_need_cs_space for checking the memory usage
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*
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* - if r600_need_dma_space has been called for the buffer
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*
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* - when emitting state packets and draw packets (because preceding packets
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* can't be re-emitted at that point)
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*
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* - if shader resource "enabled_mask" is not up-to-date or there is
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* a different constraint disallowing a context flush
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*/
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static inline unsigned
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radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
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struct r600_ring *ring,
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struct r600_resource *rbo,
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unsigned usage,
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bool check_mem)
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{
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if (check_mem &&
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!radeon_cs_memory_below_limit(rctx->screen, &ring->cs,
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rctx->vram + rbo->vram_usage,
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rctx->gtt + rbo->gart_usage))
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ring->flush(rctx, PIPE_FLUSH_ASYNC, NULL);
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return radeon_add_to_buffer_list(rctx, ring, rbo, usage);
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}
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static inline void r600_emit_reloc(struct r600_common_context *rctx,
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struct r600_ring *ring, struct r600_resource *rbo,
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unsigned usage)
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{
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struct radeon_cmdbuf *cs = &ring->cs;
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bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.r600_has_virtual_memory;
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unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage);
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if (!has_vm) {
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc);
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}
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}
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static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg < R600_CONTEXT_REG_OFFSET);
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assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
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radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
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}
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static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_config_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= R600_CONTEXT_REG_OFFSET);
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assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
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radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
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}
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static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_context_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
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unsigned reg, unsigned idx,
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unsigned value)
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{
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assert(reg >= R600_CONTEXT_REG_OFFSET);
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assert(cs->current.cdw + 3 <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
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radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
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radeon_emit(cs, value);
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}
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static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
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assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
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radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
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}
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static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_sh_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
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assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
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radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
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}
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static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_uconfig_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
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unsigned reg, unsigned idx,
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unsigned value)
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{
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assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
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assert(cs->current.cdw + 3 <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
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radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
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radeon_emit(cs, value);
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}
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#endif
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