362 lines
9.1 KiB
XML
362 lines
9.1 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright © 2020 Google, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice (including the next
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paragraph) shall be included in all copies or substantial portions of the
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Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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-->
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<isa>
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<!--
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Helpers for cat2/cat3 nop encoding, which re-uses the SRC1_R/SRC2_R
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fields to encode a # of nop delay slots following the instruction.
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-->
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<expr name="#cat2-cat3-nop-encoding">
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(({SRC1_R} != 0) || ({SRC2_R} != 0)) && ({REPEAT} == 0)
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</expr>
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<expr name="#cat2-cat3-nop-value">
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{SRC1_R} | ({SRC2_R} << 1)
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</expr>
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<!--
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Source/Dest gpr encoding. In the gpr case, this handles the special
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cases (p0.x/a0.x)
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-->
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<expr name="#reg-gpr-a0">
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{GPR} == 61 /* a0.* */
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</expr>
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<expr name="#reg-gpr-p0">
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{GPR} == 62 /* p0.x */
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</expr>
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<bitset name="#reg-gpr" size="8">
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<override expr="#reg-gpr-a0">
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<display>
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a0.{SWIZ}
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</display>
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<assert low="2" high="7">111101</assert>
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</override>
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<override expr="#reg-gpr-p0">
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<display>
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p0.{SWIZ}
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</display>
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<assert low="2" high="7">111110</assert>
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</override>
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<display>
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r{GPR}.{SWIZ}
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</display>
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<field name="SWIZ" low="0" high="1" type="#swiz"/>
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<field name="GPR" low="2" high="7" type="uint"/>
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<encode type="struct ir3_register *">
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<map name="GPR">src->num >> 2</map>
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<map name="SWIZ">src->num & 0x3</map>
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</encode>
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</bitset>
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<bitset name="#reg-const" size="11">
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<display>
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c{CONST}.{SWIZ}
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</display>
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<field name="SWIZ" low="0" high="1" type="#swiz"/>
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<field name="CONST" low="2" high="10" type="uint"/>
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<encode type="struct ir3_register *">
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<map name="CONST">src->num >> 2</map>
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<map name="SWIZ">src->num & 0x3</map>
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</encode>
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</bitset>
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<expr name="#offset-zero">
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{OFFSET} == 0
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</expr>
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<bitset name="#reg-relative-gpr" size="10">
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<override expr="#offset-zero">
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<display>
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r<a0.x>
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</display>
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</override>
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<display>
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r<a0.x + {OFFSET}>
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</display>
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<field name="OFFSET" low="0" high="9" type="int"/>
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<encode type="struct ir3_register *">
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<map name="OFFSET">src->array.offset</map>
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</encode>
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</bitset>
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<bitset name="#reg-relative-const" size="10">
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<override expr="#offset-zero">
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<display>
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c<a0.x>
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</display>
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</override>
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<display>
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c<a0.x + {OFFSET}>
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</display>
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<field name="OFFSET" low="0" high="9" type="int"/>
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<encode type="struct ir3_register *">
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<map name="OFFSET">src->array.offset</map>
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</encode>
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</bitset>
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<!--
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Source Register encoding, used in cat2 and cat4 where a src can be
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either gpr/const/relative
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-->
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<bitset name="#multisrc" size="16">
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<doc>
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Encoding for instruction source which can be GPR/CONST/IMMED
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or relative GPR/CONST.
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</doc>
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<encode type="struct ir3_register *" case-prefix="REG_">
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<map name="ABSNEG">extract_ABSNEG(src)</map>
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<map name="SRC">src</map>
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</encode>
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</bitset>
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<bitset name="#mulitsrc-immed" extends="#multisrc">
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<override expr="#multisrc-half">
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<display>
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{ABSNEG}{SRC_R}h({IMMED})
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</display>
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</override>
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<display>
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{ABSNEG}{SRC_R}{IMMED}
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</display>
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<field name="IMMED" low="0" high="10" type="int"/>
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<pattern low="11" high="13">100</pattern>
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<field name="ABSNEG" low="14" high="15" type="#absneg"/>
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<encode>
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<map name="IMMED">extract_reg_iim(src)</map>
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</encode>
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</bitset>
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<bitset name="#mulitsrc-immed-flut" extends="#multisrc">
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<doc>
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Immediate with int->float lookup table:
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0 -> 0.0
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1 -> 0.5
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2 -> 1.0
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3 -> 2.0
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4 -> e
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5 -> pi
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6 -> 1/pi
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7 -> 1/log2(e)
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8 -> log2(e)
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9 -> 1/log2(10)
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10 -> log2(10)
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11 -> 4.0
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</doc>
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<field name="IMMED" low="0" high="9" type="#flut"/>
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<pattern low="11" high="13">101</pattern>
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<field name="ABSNEG" low="14" high="15" type="#absneg"/>
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<encode>
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<map name="IMMED">extract_reg_uim(src)</map>
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</encode>
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</bitset>
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<bitset name="#multisrc-immed-flut-full" extends="#mulitsrc-immed-flut">
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<display>
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{ABSNEG}{SRC_R}{IMMED}
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</display>
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<pattern pos="10">0</pattern>
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</bitset>
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<bitset name="#multisrc-immed-flut-half" extends="#mulitsrc-immed-flut">
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<display>
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{ABSNEG}{SRC_R}h{IMMED}
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</display>
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<pattern pos="10">1</pattern>
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</bitset>
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<expr name="#multisrc-half">
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!{FULL}
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</expr>
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<bitset name="#multisrc-gpr" extends="#multisrc">
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<display>
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{ABSNEG}{SRC_R}{HALF}{SRC}
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</display>
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<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
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<field name="SRC" low="0" high="7" type="#reg-gpr"/>
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<pattern low="8" high="13">000000</pattern>
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<field name="ABSNEG" low="14" high="15" type="#absneg"/>
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</bitset>
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<bitset name="#multisrc-const" extends="#multisrc">
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<display>
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{ABSNEG}{SRC_R}{HALF}{SRC}
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</display>
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<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
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<field name="SRC" low="0" high="10" type="#reg-const"/>
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<pattern low="11" high="13">x10</pattern>
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<field name="ABSNEG" low="14" high="15" type="#absneg"/>
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</bitset>
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<bitset name="#multisrc-relative" extends="#multisrc">
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<pattern low="11" high="13">001</pattern>
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<field name="ABSNEG" low="14" high="15" type="#absneg"/>
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</bitset>
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<bitset name="#multisrc-relative-gpr" extends="#multisrc-relative">
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<display>
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{ABSNEG}{SRC_R}{HALF}{SRC}
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</display>
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<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
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<field name="SRC" low="0" high="9" type="#reg-relative-gpr"/>
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<pattern pos="10">0</pattern>
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</bitset>
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<bitset name="#multisrc-relative-const" extends="#multisrc-relative">
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<display>
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{ABSNEG}{SRC_R}{HALF}{SRC}
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</display>
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<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
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<field name="SRC" low="0" high="9" type="#reg-relative-const"/>
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<pattern pos="10">1</pattern>
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</bitset>
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<!--
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For cat2/cat4, the dst reg is full precision if {FULL} == {DEST_CONV}
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In addition, for cat2 instructions that can write p0.x (cmps.*, and.b,
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xor.b, etc), p0.x is never half (DEST_CONV is ignored)
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-->
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<expr name="#dest-half">
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({FULL} == {DST_CONV}) && ({DST} <= 0xf7 /* p0.x */)
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</expr>
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<expr name="#true">
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1
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</expr>
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<expr name="#false">
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0
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</expr>
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<!-- These make #true/#false a bit redundant, but I guess keep them for clarity -->
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<expr name="#zero">
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0
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</expr>
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<expr name="#one">
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1
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</expr>
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<expr name="#two">
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2
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</expr>
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<!--
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Enums used in various places:
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-->
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<enum name="#rptN">
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<value val="0" display=""/>
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<value val="1" display="(rpt1)"/>
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<value val="2" display="(rpt2)"/>
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<value val="3" display="(rpt3)"/>
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<value val="4" display="(rpt4)"/>
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<value val="5" display="(rpt5)"/>
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</enum>
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<enum name="#cond">
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<value val="0" display="lt"/>
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<value val="1" display="le"/>
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<value val="2" display="gt"/>
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<value val="3" display="ge"/>
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<value val="4" display="eq"/>
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<value val="5" display="ne"/>
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</enum>
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<enum name="#swiz">
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<value val="0" display="x"/>
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<value val="1" display="y"/>
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<value val="2" display="z"/>
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<value val="3" display="w"/>
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</enum>
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<enum name="#type">
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<value val="0" display="f16"/>
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<value val="1" display="f32"/>
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<value val="2" display="u16"/>
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<value val="3" display="u32"/>
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<value val="4" display="s16"/>
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<value val="5" display="s32"/>
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<value val="6" display="u8"/>
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<value val="7" display="s8"/>
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</enum>
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<expr name="#type-half">
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({TYPE} == 0) /* f16 */ ||
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({TYPE} == 2) /* u16 */ ||
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({TYPE} == 4) /* s16 */ ||
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({TYPE} == 6) /* u8 */ ||
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({TYPE} == 7) /* s8 */
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</expr>
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<enum name="#absneg">
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<value val="0" display=""/>
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<value val="1" display="(neg)"/>
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<value val="2" display="(abs)"/>
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<value val="3" display="(absneg)"/>
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</enum>
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<enum name="#flut">
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<doc>int to float lookup table</doc>
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<value val="0" display="(0.0)"/>
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<value val="1" display="(0.5)"/>
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<value val="2" display="(1.0)"/>
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<value val="3" display="(2.0)"/>
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<value val="4" display="(e)"/>
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<value val="5" display="(pi)"/>
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<value val="6" display="(1/pi)"/>
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<value val="7" display="(1/log2(e))"/>
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<value val="8" display="(log2(e))"/>
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<value val="9" display="(1/log2(10))"/>
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<value val="10" display="(log2(10))"/>
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<value val="11" display="(4.0)"/>
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</enum>
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<enum name="#wrmask">
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<value val="0" display=""/>
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<value val="1" display="x"/>
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<value val="2" display="y"/>
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<value val="3" display="xy"/>
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<value val="4" display="z"/>
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<value val="5" display="zx"/>
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<value val="6" display="zy"/>
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<value val="7" display="xyz"/>
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<value val="8" display="w"/>
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<value val="9" display="xw"/>
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<value val="10" display="yw"/>
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<value val="11" display="xyw"/>
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<value val="12" display="zw"/>
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<value val="13" display="xzw"/>
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<value val="14" display="yzw"/>
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<value val="15" display="xyzw"/>
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</enum>
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</isa>
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