248 lines
7.5 KiB
C
248 lines
7.5 KiB
C
/*
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* Copyright © 2019 Igalia S.L.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "ir3_nir.h"
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/**
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* A pass which detects tex instructions which are candidate to be executed
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* prior to FS shader start, and change them to nir_texop_tex_prefetch.
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*/
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static int
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coord_offset(nir_ssa_def *ssa)
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{
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nir_instr *parent_instr = ssa->parent_instr;
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/* The coordinate of a texture sampling instruction eligible for
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* pre-fetch is either going to be a load_interpolated_input/
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* load_input, or a vec2 assembling non-swizzled components of
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* a load_interpolated_input/load_input (due to varying packing)
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*/
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if (parent_instr->type == nir_instr_type_alu) {
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nir_alu_instr *alu = nir_instr_as_alu(parent_instr);
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if (alu->op != nir_op_vec2)
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return -1;
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if (!alu->src[0].src.is_ssa)
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return -1;
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int base_offset =
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coord_offset(alu->src[0].src.ssa) + alu->src[0].swizzle[0];
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/* NOTE it might be possible to support more than 2D? */
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for (int i = 1; i < 2; i++) {
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if (!alu->src[i].src.is_ssa)
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return -1;
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int nth_offset =
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coord_offset(alu->src[i].src.ssa) + alu->src[i].swizzle[0];
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if (nth_offset != (base_offset + i))
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return -1;
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}
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return base_offset;
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}
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if (parent_instr->type != nir_instr_type_intrinsic)
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return -1;
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nir_intrinsic_instr *input = nir_instr_as_intrinsic(parent_instr);
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if (input->intrinsic != nir_intrinsic_load_interpolated_input)
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return -1;
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/* limit to load_barycentric_pixel, other interpolation modes don't seem
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* to be supported:
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*/
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if (!input->src[0].is_ssa)
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return -1;
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nir_intrinsic_instr *interp =
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nir_instr_as_intrinsic(input->src[0].ssa->parent_instr);
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if (interp->intrinsic != nir_intrinsic_load_barycentric_pixel)
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return -1;
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/* we also need a const input offset: */
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if (!nir_src_is_const(input->src[1]))
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return -1;
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unsigned base = nir_src_as_uint(input->src[1]) + nir_intrinsic_base(input);
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unsigned comp = nir_intrinsic_component(input);
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return (4 * base) + comp;
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}
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int
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ir3_nir_coord_offset(nir_ssa_def *ssa)
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{
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assert(ssa->num_components == 2);
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return coord_offset(ssa);
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}
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static bool
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has_src(nir_tex_instr *tex, nir_tex_src_type type)
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{
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return nir_tex_instr_src_index(tex, type) >= 0;
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}
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static bool
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ok_bindless_src(nir_tex_instr *tex, nir_tex_src_type type)
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{
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int idx = nir_tex_instr_src_index(tex, type);
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assert(idx >= 0);
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nir_intrinsic_instr *bindless = ir3_bindless_resource(tex->src[idx].src);
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/* TODO from SP_FS_BINDLESS_PREFETCH[n] it looks like this limit should
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* be 1<<8 ?
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*/
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return nir_src_is_const(bindless->src[0]) &&
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(nir_src_as_uint(bindless->src[0]) < (1 << 16));
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}
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/**
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* Check that we will be able to encode the tex/samp parameters
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* successfully. These limits are based on the layout of
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* SP_FS_PREFETCH[n] and SP_FS_BINDLESS_PREFETCH[n], so at some
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* point (if those regs changes) they may become generation
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* specific.
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*/
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static bool
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ok_tex_samp(nir_tex_instr *tex)
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{
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if (has_src(tex, nir_tex_src_texture_handle)) {
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/* bindless case: */
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assert(has_src(tex, nir_tex_src_sampler_handle));
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return ok_bindless_src(tex, nir_tex_src_texture_handle) &&
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ok_bindless_src(tex, nir_tex_src_sampler_handle);
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} else {
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assert(!has_src(tex, nir_tex_src_texture_offset));
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assert(!has_src(tex, nir_tex_src_sampler_offset));
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return (tex->texture_index <= 0x1f) && (tex->sampler_index <= 0xf);
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}
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}
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static bool
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lower_tex_prefetch_block(nir_block *block)
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{
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bool progress = false;
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nir_foreach_instr_safe (instr, block) {
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if (instr->type != nir_instr_type_tex)
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continue;
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nir_tex_instr *tex = nir_instr_as_tex(instr);
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if (tex->op != nir_texop_tex)
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continue;
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if (has_src(tex, nir_tex_src_bias) || has_src(tex, nir_tex_src_lod) ||
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has_src(tex, nir_tex_src_comparator) ||
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has_src(tex, nir_tex_src_projector) ||
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has_src(tex, nir_tex_src_offset) || has_src(tex, nir_tex_src_ddx) ||
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has_src(tex, nir_tex_src_ddy) || has_src(tex, nir_tex_src_ms_index) ||
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has_src(tex, nir_tex_src_texture_offset) ||
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has_src(tex, nir_tex_src_sampler_offset))
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continue;
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/* only prefetch for simple 2d tex fetch case */
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if (tex->sampler_dim != GLSL_SAMPLER_DIM_2D || tex->is_array)
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continue;
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if (!ok_tex_samp(tex))
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continue;
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int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
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/* First source should be the sampling coordinate. */
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nir_tex_src *coord = &tex->src[idx];
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assert(coord->src.is_ssa);
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if (ir3_nir_coord_offset(coord->src.ssa) >= 0) {
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tex->op = nir_texop_tex_prefetch;
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progress |= true;
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}
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}
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return progress;
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}
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static bool
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lower_tex_prefetch_func(nir_function_impl *impl)
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{
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/* Only instructions in the the outer-most block are considered eligible for
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* pre-dispatch, because they need to be move-able to the beginning of the
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* shader to avoid locking down the register holding the pre-fetched result
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* for too long. However if there is a preamble we should skip the preamble
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* and only look in the first block after the preamble instead, because that
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* corresponds to the first block in the original program and texture fetches
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* in the preamble are never pre-dispatchable.
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*/
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nir_block *block = nir_start_block(impl);
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nir_if *nif = nir_block_get_following_if(block);
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if (nif) {
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nir_instr *cond = nif->condition.ssa->parent_instr;
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if (cond->type == nir_instr_type_intrinsic &&
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nir_instr_as_intrinsic(cond)->intrinsic ==
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nir_intrinsic_preamble_start_ir3) {
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block = nir_cf_node_as_block(nir_cf_node_next(&nif->cf_node));
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}
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}
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bool progress = lower_tex_prefetch_block(block);
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if (progress) {
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nir_metadata_preserve(impl,
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nir_metadata_block_index | nir_metadata_dominance);
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}
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return progress;
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}
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bool
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ir3_nir_lower_tex_prefetch(nir_shader *shader)
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{
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bool progress = false;
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assert(shader->info.stage == MESA_SHADER_FRAGMENT);
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nir_foreach_function (function, shader) {
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/* Only texture sampling instructions inside the main function
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* are eligible for pre-dispatch.
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*/
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if (!function->impl || !function->is_entrypoint)
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continue;
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progress |= lower_tex_prefetch_func(function->impl);
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}
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return progress;
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}
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