347 lines
12 KiB
C
347 lines
12 KiB
C
/*
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* Copyright © 2018-2019 Igalia S.L.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "compiler/nir/nir_builder.h"
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#include "ir3_nir.h"
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/**
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* This pass moves to NIR certain offset computations for different I/O
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* ops that are currently implemented on the IR3 backend compiler, to
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* give NIR a chance to optimize them:
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*
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* - Dword-offset for SSBO load, store and atomics: A new, similar intrinsic
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* is emitted that replaces the original one, adding a new source that
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* holds the result of the original byte-offset source divided by 4.
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*/
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/* Returns the ir3-specific intrinsic opcode corresponding to an SSBO
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* instruction that is handled by this pass. It also conveniently returns
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* the offset source index in @offset_src_idx.
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*
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* If @intrinsic is not SSBO, or it is not handled by the pass, -1 is
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* returned.
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*/
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static int
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get_ir3_intrinsic_for_ssbo_intrinsic(unsigned intrinsic,
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uint8_t *offset_src_idx)
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{
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assert(offset_src_idx);
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*offset_src_idx = 1;
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switch (intrinsic) {
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case nir_intrinsic_store_ssbo:
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*offset_src_idx = 2;
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return nir_intrinsic_store_ssbo_ir3;
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case nir_intrinsic_load_ssbo:
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return nir_intrinsic_load_ssbo_ir3;
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case nir_intrinsic_ssbo_atomic_add:
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return nir_intrinsic_ssbo_atomic_add_ir3;
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case nir_intrinsic_ssbo_atomic_imin:
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return nir_intrinsic_ssbo_atomic_imin_ir3;
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case nir_intrinsic_ssbo_atomic_umin:
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return nir_intrinsic_ssbo_atomic_umin_ir3;
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case nir_intrinsic_ssbo_atomic_imax:
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return nir_intrinsic_ssbo_atomic_imax_ir3;
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case nir_intrinsic_ssbo_atomic_umax:
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return nir_intrinsic_ssbo_atomic_umax_ir3;
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case nir_intrinsic_ssbo_atomic_and:
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return nir_intrinsic_ssbo_atomic_and_ir3;
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case nir_intrinsic_ssbo_atomic_or:
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return nir_intrinsic_ssbo_atomic_or_ir3;
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case nir_intrinsic_ssbo_atomic_xor:
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return nir_intrinsic_ssbo_atomic_xor_ir3;
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case nir_intrinsic_ssbo_atomic_exchange:
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return nir_intrinsic_ssbo_atomic_exchange_ir3;
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case nir_intrinsic_ssbo_atomic_comp_swap:
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return nir_intrinsic_ssbo_atomic_comp_swap_ir3;
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default:
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break;
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}
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return -1;
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}
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static nir_ssa_def *
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check_and_propagate_bit_shift32(nir_builder *b, nir_alu_instr *alu_instr,
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int32_t direction, int32_t shift)
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{
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assert(alu_instr->src[1].src.is_ssa);
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nir_ssa_def *shift_ssa = alu_instr->src[1].src.ssa;
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/* Only propagate if the shift is a const value so we can check value range
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* statically.
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*/
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nir_const_value *const_val = nir_src_as_const_value(alu_instr->src[1].src);
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if (!const_val)
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return NULL;
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int32_t current_shift = const_val[0].i32 * direction;
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int32_t new_shift = current_shift + shift;
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/* If the merge would reverse the direction, bail out.
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* e.g, 'x << 2' then 'x >> 4' is not 'x >> 2'.
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*/
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if (current_shift * new_shift < 0)
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return NULL;
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/* If the propagation would overflow an int32_t, bail out too to be on the
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* safe side.
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*/
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if (new_shift < -31 || new_shift > 31)
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return NULL;
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/* Add or substract shift depending on the final direction (SHR vs. SHL). */
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if (shift * direction < 0)
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shift_ssa = nir_isub(b, shift_ssa, nir_imm_int(b, abs(shift)));
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else
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shift_ssa = nir_iadd(b, shift_ssa, nir_imm_int(b, abs(shift)));
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return shift_ssa;
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}
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nir_ssa_def *
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ir3_nir_try_propagate_bit_shift(nir_builder *b, nir_ssa_def *offset,
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int32_t shift)
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{
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nir_instr *offset_instr = offset->parent_instr;
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if (offset_instr->type != nir_instr_type_alu)
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return NULL;
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nir_alu_instr *alu = nir_instr_as_alu(offset_instr);
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nir_ssa_def *shift_ssa;
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nir_ssa_def *new_offset = NULL;
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/* the first src could be something like ssa_18.x, but we only want
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* the single component. Otherwise the ishl/ishr/ushr could turn
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* into a vec4 operation:
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*/
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nir_ssa_def *src0 = nir_mov_alu(b, alu->src[0], 1);
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switch (alu->op) {
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case nir_op_ishl:
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shift_ssa = check_and_propagate_bit_shift32(b, alu, 1, shift);
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if (shift_ssa)
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new_offset = nir_ishl(b, src0, shift_ssa);
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break;
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case nir_op_ishr:
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shift_ssa = check_and_propagate_bit_shift32(b, alu, -1, shift);
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if (shift_ssa)
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new_offset = nir_ishr(b, src0, shift_ssa);
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break;
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case nir_op_ushr:
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shift_ssa = check_and_propagate_bit_shift32(b, alu, -1, shift);
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if (shift_ssa)
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new_offset = nir_ushr(b, src0, shift_ssa);
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break;
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default:
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return NULL;
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}
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return new_offset;
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}
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/* isam doesn't have an "untyped" field, so it can only load 1 component at a
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* time because our storage buffer descriptors use a 1-component format.
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* Therefore we need to scalarize any loads that would use isam.
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*/
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static void
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scalarize_load(nir_intrinsic_instr *intrinsic, nir_builder *b)
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{
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struct nir_ssa_def *results[NIR_MAX_VEC_COMPONENTS];
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nir_ssa_def *descriptor = intrinsic->src[0].ssa;
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nir_ssa_def *offset = intrinsic->src[1].ssa;
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nir_ssa_def *new_offset = intrinsic->src[2].ssa;
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unsigned comp_size = intrinsic->dest.ssa.bit_size / 8;
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for (unsigned i = 0; i < intrinsic->dest.ssa.num_components; i++) {
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results[i] =
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nir_load_ssbo_ir3(b, 1, intrinsic->dest.ssa.bit_size, descriptor,
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nir_iadd(b, offset, nir_imm_int(b, i * comp_size)),
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nir_iadd(b, new_offset, nir_imm_int(b, i)),
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.access = nir_intrinsic_access(intrinsic),
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.align_mul = nir_intrinsic_align_mul(intrinsic),
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.align_offset = nir_intrinsic_align_offset(intrinsic));
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}
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nir_ssa_def *result = nir_vec(b, results, intrinsic->dest.ssa.num_components);
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nir_ssa_def_rewrite_uses(&intrinsic->dest.ssa, result);
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nir_instr_remove(&intrinsic->instr);
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}
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static bool
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lower_offset_for_ssbo(nir_intrinsic_instr *intrinsic, nir_builder *b,
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unsigned ir3_ssbo_opcode, uint8_t offset_src_idx)
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{
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unsigned num_srcs = nir_intrinsic_infos[intrinsic->intrinsic].num_srcs;
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int shift = 2;
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bool has_dest = nir_intrinsic_infos[intrinsic->intrinsic].has_dest;
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nir_ssa_def *new_dest = NULL;
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/* for 16-bit ssbo access, offset is in 16-bit words instead of dwords */
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if ((has_dest && intrinsic->dest.ssa.bit_size == 16) ||
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(!has_dest && intrinsic->src[0].ssa->bit_size == 16))
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shift = 1;
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/* Here we create a new intrinsic and copy over all contents from the old
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* one. */
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nir_intrinsic_instr *new_intrinsic;
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nir_src *target_src;
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b->cursor = nir_before_instr(&intrinsic->instr);
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/* 'offset_src_idx' holds the index of the source that represent the offset. */
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new_intrinsic = nir_intrinsic_instr_create(b->shader, ir3_ssbo_opcode);
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assert(intrinsic->src[offset_src_idx].is_ssa);
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nir_ssa_def *offset = intrinsic->src[offset_src_idx].ssa;
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/* Since we don't have value range checking, we first try to propagate
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* the division by 4 ('offset >> 2') into another bit-shift instruction that
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* possibly defines the offset. If that's the case, we emit a similar
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* instructions adjusting (merging) the shift value.
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*
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* Here we use the convention that shifting right is negative while shifting
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* left is positive. So 'x / 4' ~ 'x >> 2' or 'x << -2'.
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*/
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nir_ssa_def *new_offset = ir3_nir_try_propagate_bit_shift(b, offset, -shift);
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/* The new source that will hold the dword-offset is always the last
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* one for every intrinsic.
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*/
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target_src = &new_intrinsic->src[num_srcs];
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*target_src = nir_src_for_ssa(offset);
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if (has_dest) {
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assert(intrinsic->dest.is_ssa);
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nir_ssa_def *dest = &intrinsic->dest.ssa;
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nir_ssa_dest_init(&new_intrinsic->instr, &new_intrinsic->dest,
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dest->num_components, dest->bit_size, NULL);
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new_dest = &new_intrinsic->dest.ssa;
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}
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for (unsigned i = 0; i < num_srcs; i++)
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new_intrinsic->src[i] = nir_src_for_ssa(intrinsic->src[i].ssa);
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nir_intrinsic_copy_const_indices(new_intrinsic, intrinsic);
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new_intrinsic->num_components = intrinsic->num_components;
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/* If we managed to propagate the division by 4, just use the new offset
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* register and don't emit the SHR.
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*/
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if (new_offset)
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offset = new_offset;
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else
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offset = nir_ushr(b, offset, nir_imm_int(b, shift));
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/* Insert the new intrinsic right before the old one. */
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nir_builder_instr_insert(b, &new_intrinsic->instr);
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/* Replace the last source of the new intrinsic by the result of
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* the offset divided by 4.
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*/
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nir_instr_rewrite_src(&new_intrinsic->instr, target_src,
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nir_src_for_ssa(offset));
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if (has_dest) {
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/* Replace the uses of the original destination by that
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* of the new intrinsic.
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*/
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nir_ssa_def_rewrite_uses(&intrinsic->dest.ssa, new_dest);
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}
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/* Finally remove the original intrinsic. */
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nir_instr_remove(&intrinsic->instr);
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if (new_intrinsic->intrinsic == nir_intrinsic_load_ssbo_ir3 &&
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(nir_intrinsic_access(new_intrinsic) & ACCESS_CAN_REORDER) &&
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ir3_bindless_resource(new_intrinsic->src[0]) &&
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new_intrinsic->num_components > 1)
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scalarize_load(new_intrinsic, b);
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return true;
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}
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static bool
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lower_io_offsets_block(nir_block *block, nir_builder *b, void *mem_ctx)
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{
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bool progress = false;
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nir_foreach_instr_safe (instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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/* SSBO */
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int ir3_intrinsic;
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uint8_t offset_src_idx;
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ir3_intrinsic =
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get_ir3_intrinsic_for_ssbo_intrinsic(intr->intrinsic, &offset_src_idx);
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if (ir3_intrinsic != -1) {
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progress |= lower_offset_for_ssbo(intr, b, (unsigned)ir3_intrinsic,
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offset_src_idx);
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}
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}
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return progress;
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}
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static bool
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lower_io_offsets_func(nir_function_impl *impl)
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{
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void *mem_ctx = ralloc_parent(impl);
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nir_builder b;
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nir_builder_init(&b, impl);
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bool progress = false;
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nir_foreach_block_safe (block, impl) {
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progress |= lower_io_offsets_block(block, &b, mem_ctx);
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}
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if (progress) {
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nir_metadata_preserve(impl,
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nir_metadata_block_index | nir_metadata_dominance);
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}
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return progress;
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}
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bool
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ir3_nir_lower_io_offsets(nir_shader *shader)
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{
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bool progress = false;
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nir_foreach_function (function, shader) {
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if (function->impl)
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progress |= lower_io_offsets_func(function->impl);
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}
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return progress;
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}
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