717 lines
23 KiB
C
717 lines
23 KiB
C
/*
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* Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include <math.h>
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#include "util/half_float.h"
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#include "util/u_math.h"
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#include "ir3.h"
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#include "ir3_compiler.h"
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#include "ir3_shader.h"
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#define swap(a, b) \
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do { \
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__typeof(a) __tmp = (a); \
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(a) = (b); \
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(b) = __tmp; \
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} while (0)
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/*
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* Copy Propagate:
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*/
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struct ir3_cp_ctx {
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struct ir3 *shader;
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struct ir3_shader_variant *so;
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bool progress;
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};
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/* is it a type preserving mov, with ok flags?
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*
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* @instr: the mov to consider removing
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* @dst_instr: the instruction consuming the mov (instr)
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*
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* TODO maybe drop allow_flags since this is only false when dst is
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* NULL (ie. outputs)
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*/
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static bool
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is_eligible_mov(struct ir3_instruction *instr,
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struct ir3_instruction *dst_instr, bool allow_flags)
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{
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if (is_same_type_mov(instr)) {
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struct ir3_register *dst = instr->dsts[0];
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struct ir3_register *src = instr->srcs[0];
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struct ir3_instruction *src_instr = ssa(src);
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/* only if mov src is SSA (not const/immed): */
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if (!src_instr)
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return false;
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/* no indirect: */
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if (dst->flags & IR3_REG_RELATIV)
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return false;
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if (src->flags & IR3_REG_RELATIV)
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return false;
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if (src->flags & IR3_REG_ARRAY)
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return false;
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if (!allow_flags)
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if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG | IR3_REG_SABS |
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IR3_REG_SNEG | IR3_REG_BNOT))
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return false;
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return true;
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}
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return false;
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}
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/* we can end up with extra cmps.s from frontend, which uses a
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*
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* cmps.s p0.x, cond, 0
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*
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* as a way to mov into the predicate register. But frequently 'cond'
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* is itself a cmps.s/cmps.f/cmps.u. So detect this special case.
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*/
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static bool
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is_foldable_double_cmp(struct ir3_instruction *cmp)
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{
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struct ir3_instruction *cond = ssa(cmp->srcs[0]);
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return (cmp->dsts[0]->num == regid(REG_P0, 0)) && cond &&
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(cmp->srcs[1]->flags & IR3_REG_IMMED) &&
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(cmp->srcs[1]->iim_val == 0) &&
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(cmp->cat2.condition == IR3_COND_NE) &&
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(!cond->address || cond->address->def->instr->block == cmp->block);
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}
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/* propagate register flags from src to dst.. negates need special
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* handling to cancel each other out.
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*/
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static void
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combine_flags(unsigned *dstflags, struct ir3_instruction *src)
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{
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unsigned srcflags = src->srcs[0]->flags;
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/* if what we are combining into already has (abs) flags,
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* we can drop (neg) from src:
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*/
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if (*dstflags & IR3_REG_FABS)
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srcflags &= ~IR3_REG_FNEG;
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if (*dstflags & IR3_REG_SABS)
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srcflags &= ~IR3_REG_SNEG;
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if (srcflags & IR3_REG_FABS)
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*dstflags |= IR3_REG_FABS;
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if (srcflags & IR3_REG_SABS)
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*dstflags |= IR3_REG_SABS;
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if (srcflags & IR3_REG_FNEG)
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*dstflags ^= IR3_REG_FNEG;
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if (srcflags & IR3_REG_SNEG)
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*dstflags ^= IR3_REG_SNEG;
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if (srcflags & IR3_REG_BNOT)
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*dstflags ^= IR3_REG_BNOT;
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*dstflags &= ~IR3_REG_SSA;
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*dstflags |= srcflags & IR3_REG_SSA;
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*dstflags |= srcflags & IR3_REG_CONST;
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*dstflags |= srcflags & IR3_REG_IMMED;
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*dstflags |= srcflags & IR3_REG_RELATIV;
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*dstflags |= srcflags & IR3_REG_ARRAY;
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*dstflags |= srcflags & IR3_REG_SHARED;
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/* if src of the src is boolean we can drop the (abs) since we know
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* the source value is already a postitive integer. This cleans
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* up the absnegs that get inserted when converting between nir and
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* native boolean (see ir3_b2n/n2b)
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*/
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struct ir3_instruction *srcsrc = ssa(src->srcs[0]);
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if (srcsrc && is_bool(srcsrc))
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*dstflags &= ~IR3_REG_SABS;
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}
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/* Tries lowering an immediate register argument to a const buffer access by
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* adding to the list of immediates to be pushed to the const buffer when
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* switching to this shader.
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*/
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static bool
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lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n,
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struct ir3_register *reg, unsigned new_flags)
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{
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if (!(new_flags & IR3_REG_IMMED))
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return false;
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new_flags &= ~IR3_REG_IMMED;
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new_flags |= IR3_REG_CONST;
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if (!ir3_valid_flags(instr, n, new_flags))
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return false;
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reg = ir3_reg_clone(ctx->shader, reg);
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/* Half constant registers seems to handle only 32-bit values
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* within floating-point opcodes. So convert back to 32-bit values.
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*/
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bool f_opcode =
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(is_cat2_float(instr->opc) || is_cat3_float(instr->opc)) ? true : false;
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if (f_opcode && (new_flags & IR3_REG_HALF))
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reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
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/* in some cases, there are restrictions on (abs)/(neg) plus const..
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* so just evaluate those and clear the flags:
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*/
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if (new_flags & IR3_REG_SABS) {
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reg->iim_val = abs(reg->iim_val);
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new_flags &= ~IR3_REG_SABS;
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}
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if (new_flags & IR3_REG_FABS) {
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reg->fim_val = fabs(reg->fim_val);
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new_flags &= ~IR3_REG_FABS;
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}
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if (new_flags & IR3_REG_SNEG) {
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reg->iim_val = -reg->iim_val;
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new_flags &= ~IR3_REG_SNEG;
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}
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if (new_flags & IR3_REG_FNEG) {
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reg->fim_val = -reg->fim_val;
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new_flags &= ~IR3_REG_FNEG;
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}
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/* Reallocate for 4 more elements whenever it's necessary. Note that ir3
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* printing relies on having groups of 4 dwords, so we fill the unused
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* slots with a dummy value.
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*/
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struct ir3_const_state *const_state = ir3_const_state(ctx->so);
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if (const_state->immediates_count == const_state->immediates_size) {
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const_state->immediates = rerzalloc(
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const_state, const_state->immediates,
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__typeof__(const_state->immediates[0]), const_state->immediates_size,
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const_state->immediates_size + 4);
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const_state->immediates_size += 4;
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for (int i = const_state->immediates_count;
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i < const_state->immediates_size; i++)
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const_state->immediates[i] = 0xd0d0d0d0;
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}
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int i;
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for (i = 0; i < const_state->immediates_count; i++) {
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if (const_state->immediates[i] == reg->uim_val)
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break;
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}
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if (i == const_state->immediates_count) {
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/* Add on a new immediate to be pushed, if we have space left in the
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* constbuf.
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*/
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if (const_state->offsets.immediate + const_state->immediates_count / 4 >=
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ir3_max_const(ctx->so))
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return false;
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const_state->immediates[i] = reg->uim_val;
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const_state->immediates_count++;
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}
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reg->flags = new_flags;
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reg->num = i + (4 * const_state->offsets.immediate);
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instr->srcs[n] = reg;
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return true;
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}
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static void
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unuse(struct ir3_instruction *instr)
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{
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assert(instr->use_count > 0);
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if (--instr->use_count == 0) {
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struct ir3_block *block = instr->block;
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instr->barrier_class = 0;
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instr->barrier_conflict = 0;
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/* we don't want to remove anything in keeps (which could
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* be things like array store's)
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*/
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for (unsigned i = 0; i < block->keeps_count; i++) {
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assert(block->keeps[i] != instr);
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}
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}
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}
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/**
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* Handles the special case of the 2nd src (n == 1) to "normal" mad
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* instructions, which cannot reference a constant. See if it is
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* possible to swap the 1st and 2nd sources.
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*/
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static bool
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try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
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{
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if (!is_mad(instr->opc))
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return false;
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/* If we've already tried, nothing more to gain.. we will only
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* have previously swapped if the original 2nd src was const or
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* immed. So swapping back won't improve anything and could
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* result in an infinite "progress" loop.
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*/
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if (instr->cat3.swapped)
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return false;
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/* cat3 doesn't encode immediate, but we can lower immediate
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* to const if that helps:
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*/
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if (new_flags & IR3_REG_IMMED) {
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new_flags &= ~IR3_REG_IMMED;
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new_flags |= IR3_REG_CONST;
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}
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/* If the reason we couldn't fold without swapping is something
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* other than const source, then swapping won't help:
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*/
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if (!(new_flags & IR3_REG_CONST))
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return false;
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instr->cat3.swapped = true;
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/* NOTE: pre-swap first two src's before valid_flags(),
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* which might try to dereference the n'th src:
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*/
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swap(instr->srcs[0], instr->srcs[1]);
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bool valid_swap =
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/* can we propagate mov if we move 2nd src to first? */
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ir3_valid_flags(instr, 0, new_flags) &&
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/* and does first src fit in second slot? */
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ir3_valid_flags(instr, 1, instr->srcs[1]->flags);
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if (!valid_swap) {
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/* put things back the way they were: */
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swap(instr->srcs[0], instr->srcs[1]);
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} /* otherwise leave things swapped */
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return valid_swap;
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}
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/* Values that are uniform inside a loop can become divergent outside
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* it if the loop has a divergent trip count. This means that we can't
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* propagate a copy of a shared to non-shared register if it would
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* make the shared reg's live range extend outside of its loop. Users
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* outside the loop would see the value for the thread(s) that last
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* exited the loop, rather than for their own thread.
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*/
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static bool
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is_valid_shared_copy(struct ir3_instruction *dst_instr,
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struct ir3_instruction *src_instr,
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struct ir3_register *src_reg)
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{
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return !(src_reg->flags & IR3_REG_SHARED) ||
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dst_instr->block->loop_id == src_instr->block->loop_id;
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}
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/**
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* Handle cp for a given src register. This additionally handles
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* the cases of collapsing immedate/const (which replace the src
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* register with a non-ssa src) or collapsing mov's from relative
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* src (which needs to also fixup the address src reference by the
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* instruction).
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*/
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static bool
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reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
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struct ir3_register *reg, unsigned n)
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{
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struct ir3_instruction *src = ssa(reg);
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if (is_eligible_mov(src, instr, true)) {
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/* simple case, no immed/const/relativ, only mov's w/ ssa src: */
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struct ir3_register *src_reg = src->srcs[0];
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unsigned new_flags = reg->flags;
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if (!is_valid_shared_copy(instr, src, src_reg))
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return false;
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combine_flags(&new_flags, src);
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if (ir3_valid_flags(instr, n, new_flags)) {
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if (new_flags & IR3_REG_ARRAY) {
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assert(!(reg->flags & IR3_REG_ARRAY));
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reg->array = src_reg->array;
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}
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reg->flags = new_flags;
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reg->def = src_reg->def;
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instr->barrier_class |= src->barrier_class;
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instr->barrier_conflict |= src->barrier_conflict;
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unuse(src);
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reg->def->instr->use_count++;
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return true;
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}
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} else if ((is_same_type_mov(src) || is_const_mov(src)) &&
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/* cannot collapse const/immed/etc into control flow: */
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opc_cat(instr->opc) != 0) {
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/* immed/const/etc cases, which require some special handling: */
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struct ir3_register *src_reg = src->srcs[0];
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unsigned new_flags = reg->flags;
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if (!is_valid_shared_copy(instr, src, src_reg))
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return false;
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if (src_reg->flags & IR3_REG_ARRAY)
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return false;
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combine_flags(&new_flags, src);
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if (!ir3_valid_flags(instr, n, new_flags)) {
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/* See if lowering an immediate to const would help. */
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if (lower_immed(ctx, instr, n, src_reg, new_flags))
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return true;
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/* special case for "normal" mad instructions, we can
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* try swapping the first two args if that fits better.
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*
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* the "plain" MAD's (ie. the ones that don't shift first
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* src prior to multiply) can swap their first two srcs if
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* src[0] is !CONST and src[1] is CONST:
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*/
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if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
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return true;
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} else {
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return false;
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}
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}
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/* Here we handle the special case of mov from
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* CONST and/or RELATIV. These need to be handled
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* specially, because in the case of move from CONST
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* there is no src ir3_instruction so we need to
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* replace the ir3_register. And in the case of
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* RELATIV we need to handle the address register
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* dependency.
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*/
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if (src_reg->flags & IR3_REG_CONST) {
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/* an instruction cannot reference two different
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* address registers:
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*/
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if ((src_reg->flags & IR3_REG_RELATIV) &&
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conflicts(instr->address, reg->def->instr->address))
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return false;
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/* These macros expand to a mov in an if statement */
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if ((src_reg->flags & IR3_REG_RELATIV) &&
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is_subgroup_cond_mov_macro(instr))
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return false;
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/* This seems to be a hw bug, or something where the timings
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* just somehow don't work out. This restriction may only
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* apply if the first src is also CONST.
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*/
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if ((opc_cat(instr->opc) == 3) && (n == 2) &&
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(src_reg->flags & IR3_REG_RELATIV) && (src_reg->array.offset == 0))
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return false;
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/* When narrowing constant from 32b to 16b, it seems
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* to work only for float. So we should do this only with
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* float opcodes.
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*/
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if (src->cat1.dst_type == TYPE_F16) {
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/* TODO: should we have a way to tell phi/collect to use a
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* float move so that this is legal?
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*/
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if (is_meta(instr))
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return false;
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if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
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return false;
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if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
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return false;
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} else if (src->cat1.dst_type == TYPE_U16) {
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/* Since we set CONSTANT_DEMOTION_ENABLE, a float reference of
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* what was a U16 value read from the constbuf would incorrectly
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* do 32f->16f conversion, when we want to read a 16f value.
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*/
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if (is_cat2_float(instr->opc) || is_cat3_float(instr->opc))
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return false;
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if (instr->opc == OPC_MOV && type_float(instr->cat1.src_type))
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return false;
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}
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src_reg = ir3_reg_clone(instr->block->shader, src_reg);
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src_reg->flags = new_flags;
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instr->srcs[n] = src_reg;
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if (src_reg->flags & IR3_REG_RELATIV)
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ir3_instr_set_address(instr, reg->def->instr->address->def->instr);
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return true;
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}
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if (src_reg->flags & IR3_REG_IMMED) {
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int32_t iim_val = src_reg->iim_val;
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assert((opc_cat(instr->opc) == 1) ||
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(opc_cat(instr->opc) == 2) ||
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(opc_cat(instr->opc) == 6) ||
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is_meta(instr) ||
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(is_mad(instr->opc) && (n == 0)));
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if ((opc_cat(instr->opc) == 2) &&
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!ir3_cat2_int(instr->opc)) {
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iim_val = ir3_flut(src_reg);
|
|
if (iim_val < 0) {
|
|
/* Fall back to trying to load the immediate as a const: */
|
|
return lower_immed(ctx, instr, n, src_reg, new_flags);
|
|
}
|
|
}
|
|
|
|
if (new_flags & IR3_REG_SABS)
|
|
iim_val = abs(iim_val);
|
|
|
|
if (new_flags & IR3_REG_SNEG)
|
|
iim_val = -iim_val;
|
|
|
|
if (new_flags & IR3_REG_BNOT)
|
|
iim_val = ~iim_val;
|
|
|
|
if (ir3_valid_flags(instr, n, new_flags) &&
|
|
ir3_valid_immediate(instr, iim_val)) {
|
|
new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
|
|
src_reg = ir3_reg_clone(instr->block->shader, src_reg);
|
|
src_reg->flags = new_flags;
|
|
src_reg->iim_val = iim_val;
|
|
instr->srcs[n] = src_reg;
|
|
|
|
return true;
|
|
} else {
|
|
/* Fall back to trying to load the immediate as a const: */
|
|
return lower_immed(ctx, instr, n, src_reg, new_flags);
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/* Handle special case of eliminating output mov, and similar cases where
|
|
* there isn't a normal "consuming" instruction. In this case we cannot
|
|
* collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
|
|
* be eliminated)
|
|
*/
|
|
static struct ir3_instruction *
|
|
eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
|
|
{
|
|
if (is_eligible_mov(instr, NULL, false)) {
|
|
struct ir3_register *reg = instr->srcs[0];
|
|
if (!(reg->flags & IR3_REG_ARRAY)) {
|
|
struct ir3_instruction *src_instr = ssa(reg);
|
|
assert(src_instr);
|
|
ctx->progress = true;
|
|
return src_instr;
|
|
}
|
|
}
|
|
return instr;
|
|
}
|
|
|
|
/**
|
|
* Find instruction src's which are mov's that can be collapsed, replacing
|
|
* the mov dst with the mov src
|
|
*/
|
|
static void
|
|
instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
|
|
{
|
|
if (instr->srcs_count == 0)
|
|
return;
|
|
|
|
if (ir3_instr_check_mark(instr))
|
|
return;
|
|
|
|
/* walk down the graph from each src: */
|
|
bool progress;
|
|
do {
|
|
progress = false;
|
|
foreach_src_n (reg, n, instr) {
|
|
struct ir3_instruction *src = ssa(reg);
|
|
|
|
if (!src)
|
|
continue;
|
|
|
|
instr_cp(ctx, src);
|
|
|
|
/* TODO non-indirect access we could figure out which register
|
|
* we actually want and allow cp..
|
|
*/
|
|
if ((reg->flags & IR3_REG_ARRAY) && src->opc != OPC_META_PHI)
|
|
continue;
|
|
|
|
/* Don't CP absneg into meta instructions, that won't end well: */
|
|
if (is_meta(instr) &&
|
|
(src->opc == OPC_ABSNEG_F || src->opc == OPC_ABSNEG_S))
|
|
continue;
|
|
|
|
/* Don't CP mova and mova1 into their users */
|
|
if (writes_addr0(src) || writes_addr1(src))
|
|
continue;
|
|
|
|
progress |= reg_cp(ctx, instr, reg, n);
|
|
ctx->progress |= progress;
|
|
}
|
|
} while (progress);
|
|
|
|
/* After folding a mov's source we may wind up with a type-converting mov
|
|
* of an immediate. This happens e.g. with texture descriptors, since we
|
|
* narrow the descriptor (which may be a constant) to a half-reg in ir3.
|
|
* By converting the immediate in-place to the destination type, we can
|
|
* turn the mov into a same-type mov so that it can be further propagated.
|
|
*/
|
|
if (instr->opc == OPC_MOV && (instr->srcs[0]->flags & IR3_REG_IMMED) &&
|
|
instr->cat1.src_type != instr->cat1.dst_type &&
|
|
/* Only do uint types for now, until we generate other types of
|
|
* mov's during instruction selection.
|
|
*/
|
|
full_type(instr->cat1.src_type) == TYPE_U32 &&
|
|
full_type(instr->cat1.dst_type) == TYPE_U32) {
|
|
uint32_t uimm = instr->srcs[0]->uim_val;
|
|
if (instr->cat1.dst_type == TYPE_U16)
|
|
uimm &= 0xffff;
|
|
instr->srcs[0]->uim_val = uimm;
|
|
if (instr->dsts[0]->flags & IR3_REG_HALF)
|
|
instr->srcs[0]->flags |= IR3_REG_HALF;
|
|
else
|
|
instr->srcs[0]->flags &= ~IR3_REG_HALF;
|
|
instr->cat1.src_type = instr->cat1.dst_type;
|
|
ctx->progress = true;
|
|
}
|
|
|
|
/* Re-write the instruction writing predicate register to get rid
|
|
* of the double cmps.
|
|
*/
|
|
if ((instr->opc == OPC_CMPS_S) && is_foldable_double_cmp(instr)) {
|
|
struct ir3_instruction *cond = ssa(instr->srcs[0]);
|
|
switch (cond->opc) {
|
|
case OPC_CMPS_S:
|
|
case OPC_CMPS_F:
|
|
case OPC_CMPS_U:
|
|
instr->opc = cond->opc;
|
|
instr->flags = cond->flags;
|
|
instr->cat2 = cond->cat2;
|
|
if (cond->address)
|
|
ir3_instr_set_address(instr, cond->address->def->instr);
|
|
instr->srcs[0] = ir3_reg_clone(ctx->shader, cond->srcs[0]);
|
|
instr->srcs[1] = ir3_reg_clone(ctx->shader, cond->srcs[1]);
|
|
instr->barrier_class |= cond->barrier_class;
|
|
instr->barrier_conflict |= cond->barrier_conflict;
|
|
unuse(cond);
|
|
ctx->progress = true;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Handle converting a sam.s2en (taking samp/tex idx params via register)
|
|
* into a normal sam (encoding immediate samp/tex idx) if they are
|
|
* immediate. This saves some instructions and regs in the common case
|
|
* where we know samp/tex at compile time. This needs to be done in the
|
|
* frontend for bindless tex, though, so don't replicate it here.
|
|
*/
|
|
if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
|
|
!(instr->flags & IR3_INSTR_B) &&
|
|
!(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
|
|
/* The first src will be a collect, if both of it's
|
|
* two sources are mov from imm, then we can
|
|
*/
|
|
struct ir3_instruction *samp_tex = ssa(instr->srcs[0]);
|
|
|
|
assert(samp_tex->opc == OPC_META_COLLECT);
|
|
|
|
struct ir3_register *samp = samp_tex->srcs[0];
|
|
struct ir3_register *tex = samp_tex->srcs[1];
|
|
|
|
if ((samp->flags & IR3_REG_IMMED) && (tex->flags & IR3_REG_IMMED) &&
|
|
(samp->iim_val < 16) && (tex->iim_val < 16)) {
|
|
instr->flags &= ~IR3_INSTR_S2EN;
|
|
instr->cat5.samp = samp->iim_val;
|
|
instr->cat5.tex = tex->iim_val;
|
|
|
|
/* shuffle around the regs to remove the first src: */
|
|
instr->srcs_count--;
|
|
for (unsigned i = 0; i < instr->srcs_count; i++) {
|
|
instr->srcs[i] = instr->srcs[i + 1];
|
|
}
|
|
|
|
ctx->progress = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
bool
|
|
ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
|
|
{
|
|
struct ir3_cp_ctx ctx = {
|
|
.shader = ir,
|
|
.so = so,
|
|
};
|
|
|
|
/* This is a bit annoying, and probably wouldn't be necessary if we
|
|
* tracked a reverse link from producing instruction to consumer.
|
|
* But we need to know when we've eliminated the last consumer of
|
|
* a mov, so we need to do a pass to first count consumers of a
|
|
* mov.
|
|
*/
|
|
foreach_block (block, &ir->block_list) {
|
|
foreach_instr (instr, &block->instr_list) {
|
|
|
|
/* by the way, we don't account for false-dep's, so the CP
|
|
* pass should always happen before false-dep's are inserted
|
|
*/
|
|
assert(instr->deps_count == 0);
|
|
|
|
foreach_ssa_src (src, instr) {
|
|
src->use_count++;
|
|
}
|
|
}
|
|
}
|
|
|
|
ir3_clear_mark(ir);
|
|
|
|
foreach_block (block, &ir->block_list) {
|
|
if (block->condition) {
|
|
instr_cp(&ctx, block->condition);
|
|
block->condition = eliminate_output_mov(&ctx, block->condition);
|
|
}
|
|
|
|
for (unsigned i = 0; i < block->keeps_count; i++) {
|
|
instr_cp(&ctx, block->keeps[i]);
|
|
block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]);
|
|
}
|
|
}
|
|
|
|
return ctx.progress;
|
|
}
|