296 lines
11 KiB
C
296 lines
11 KiB
C
/*
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* Copyright (C) 2015-2018 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#ifndef IR3_CONTEXT_H_
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#define IR3_CONTEXT_H_
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#include "ir3.h"
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#include "ir3_compiler.h"
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#include "ir3_nir.h"
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/* for conditionally setting boolean flag(s): */
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#define COND(bool, val) ((bool) ? (val) : 0)
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#define DBG(fmt, ...) \
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do { \
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mesa_logd("%s:%d: " fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
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} while (0)
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/**
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* The context for compilation of a single shader.
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*/
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struct ir3_context {
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struct ir3_compiler *compiler;
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const struct ir3_context_funcs *funcs;
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struct nir_shader *s;
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struct nir_instr *cur_instr; /* current instruction, just for debug */
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struct ir3 *ir;
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struct ir3_shader_variant *so;
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/* Tables of scalar inputs/outputs. Because of the way varying packing
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* works, we could have inputs w/ fractional location, which is a bit
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* awkward to deal with unless we keep track of the split scalar in/
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* out components.
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*
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* These *only* have inputs/outputs that are touched by load_*input and
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* store_output.
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*/
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unsigned ninputs, noutputs;
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struct ir3_instruction **inputs;
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struct ir3_instruction **outputs;
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struct ir3_block *block; /* the current block */
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struct ir3_block *in_block; /* block created for shader inputs */
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nir_function_impl *impl;
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/* For fragment shaders, varyings are not actual shader inputs,
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* instead the hw passes a ij coord which is used with
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* bary.f.
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*
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* But NIR doesn't know that, it still declares varyings as
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* inputs. So we do all the input tracking normally and fix
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* things up after compile_instructions()
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*/
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struct ir3_instruction *ij[IJ_COUNT];
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/* for fragment shaders, for gl_FrontFacing and gl_FragCoord: */
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struct ir3_instruction *frag_face, *frag_coord;
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/* For vertex shaders, keep track of the system values sources */
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struct ir3_instruction *vertex_id, *basevertex, *instance_id, *base_instance,
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*draw_id, *view_index;
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/* For fragment shaders: */
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struct ir3_instruction *samp_id, *samp_mask_in;
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/* For geometry shaders: */
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struct ir3_instruction *primitive_id;
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struct ir3_instruction *gs_header;
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/* For tessellation shaders: */
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struct ir3_instruction *tcs_header;
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struct ir3_instruction *tess_coord;
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struct ir3_instruction *rel_patch_id;
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/* Compute shader inputs: */
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struct ir3_instruction *local_invocation_id, *work_group_id;
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/* mapping from nir_register to defining instruction: */
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struct hash_table *def_ht;
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unsigned num_arrays;
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/* Tracking for max level of flowcontrol (branchstack) needed
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* by a5xx+:
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*/
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unsigned stack, max_stack;
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unsigned loop_id;
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unsigned loop_depth;
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/* a common pattern for indirect addressing is to request the
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* same address register multiple times. To avoid generating
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* duplicate instruction sequences (which our backend does not
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* try to clean up, since that should be done as the NIR stage)
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* we cache the address value generated for a given src value:
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*
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* Note that we have to cache these per alignment, since same
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* src used for an array of vec1 cannot be also used for an
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* array of vec4.
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*/
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struct hash_table *addr0_ht[4];
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/* The same for a1.x. We only support immediate values for a1.x, as this
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* is the only use so far.
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*/
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struct hash_table_u64 *addr1_ht;
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struct hash_table *sel_cond_conversions;
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/* last dst array, for indirect we need to insert a var-store.
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*/
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struct ir3_instruction **last_dst;
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unsigned last_dst_n;
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/* maps nir_block to ir3_block, mostly for the purposes of
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* figuring out the blocks successors
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*/
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struct hash_table *block_ht;
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/* maps nir_block at the top of a loop to ir3_block collecting continue
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* edges.
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*/
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struct hash_table *continue_block_ht;
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/* on a4xx, bitmask of samplers which need astc+srgb workaround: */
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unsigned astc_srgb;
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/* on a4xx, per-sampler per-component swizzles, for tg4: */
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uint16_t sampler_swizzles[16];
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unsigned samples; /* bitmask of x,y sample shifts */
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unsigned max_texture_index;
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unsigned prefetch_limit;
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/* set if we encounter something we can't handle yet, so we
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* can bail cleanly and fallback to TGSI compiler f/e
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*/
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bool error;
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};
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struct ir3_context_funcs {
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void (*emit_intrinsic_load_ssbo)(struct ir3_context *ctx,
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nir_intrinsic_instr *intr,
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struct ir3_instruction **dst);
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void (*emit_intrinsic_store_ssbo)(struct ir3_context *ctx,
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nir_intrinsic_instr *intr);
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struct ir3_instruction *(*emit_intrinsic_atomic_ssbo)(
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struct ir3_context *ctx, nir_intrinsic_instr *intr);
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void (*emit_intrinsic_load_image)(struct ir3_context *ctx,
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nir_intrinsic_instr *intr,
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struct ir3_instruction **dst);
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void (*emit_intrinsic_store_image)(struct ir3_context *ctx,
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nir_intrinsic_instr *intr);
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struct ir3_instruction *(*emit_intrinsic_atomic_image)(
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struct ir3_context *ctx, nir_intrinsic_instr *intr);
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void (*emit_intrinsic_image_size)(struct ir3_context *ctx,
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nir_intrinsic_instr *intr,
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struct ir3_instruction **dst);
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void (*emit_intrinsic_load_global_ir3)(struct ir3_context *ctx,
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nir_intrinsic_instr *intr,
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struct ir3_instruction **dst);
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void (*emit_intrinsic_store_global_ir3)(struct ir3_context *ctx,
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nir_intrinsic_instr *intr);
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struct ir3_instruction *(*emit_intrinsic_atomic_global)(
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struct ir3_context *ctx, nir_intrinsic_instr *intr);
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};
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extern const struct ir3_context_funcs ir3_a4xx_funcs;
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extern const struct ir3_context_funcs ir3_a6xx_funcs;
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struct ir3_context *ir3_context_init(struct ir3_compiler *compiler,
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struct ir3_shader *shader,
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struct ir3_shader_variant *so);
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void ir3_context_free(struct ir3_context *ctx);
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struct ir3_instruction **ir3_get_dst_ssa(struct ir3_context *ctx,
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nir_ssa_def *dst, unsigned n);
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struct ir3_instruction **ir3_get_dst(struct ir3_context *ctx, nir_dest *dst,
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unsigned n);
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struct ir3_instruction *const *ir3_get_src(struct ir3_context *ctx,
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nir_src *src);
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void ir3_put_dst(struct ir3_context *ctx, nir_dest *dst);
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struct ir3_instruction *ir3_create_collect(struct ir3_block *block,
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struct ir3_instruction *const *arr,
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unsigned arrsz);
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void ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst,
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struct ir3_instruction *src, unsigned base, unsigned n);
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void ir3_handle_bindless_cat6(struct ir3_instruction *instr, nir_src rsrc);
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void ir3_handle_nonuniform(struct ir3_instruction *instr,
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nir_intrinsic_instr *intrin);
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void emit_intrinsic_image_size_tex(struct ir3_context *ctx,
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nir_intrinsic_instr *intr,
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struct ir3_instruction **dst);
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#define ir3_collect(block, ...) \
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({ \
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struct ir3_instruction *__arr[] = {__VA_ARGS__}; \
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ir3_create_collect(block, __arr, ARRAY_SIZE(__arr)); \
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})
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NORETURN void ir3_context_error(struct ir3_context *ctx, const char *format,
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...);
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#define compile_assert(ctx, cond) \
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do { \
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if (!(cond)) \
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ir3_context_error((ctx), "failed assert: " #cond "\n"); \
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} while (0)
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struct ir3_instruction *ir3_get_addr0(struct ir3_context *ctx,
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struct ir3_instruction *src, int align);
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struct ir3_instruction *ir3_get_addr1(struct ir3_context *ctx,
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unsigned const_val);
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struct ir3_instruction *ir3_get_predicate(struct ir3_context *ctx,
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struct ir3_instruction *src);
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void ir3_declare_array(struct ir3_context *ctx, nir_register *reg);
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struct ir3_array *ir3_get_array(struct ir3_context *ctx, nir_register *reg);
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struct ir3_instruction *ir3_create_array_load(struct ir3_context *ctx,
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struct ir3_array *arr, int n,
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struct ir3_instruction *address);
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void ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr,
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int n, struct ir3_instruction *src,
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struct ir3_instruction *address);
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static inline type_t
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utype_for_size(unsigned bit_size)
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{
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switch (bit_size) {
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case 32:
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return TYPE_U32;
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case 16:
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return TYPE_U16;
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case 8:
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return TYPE_U8;
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default:
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unreachable("bad bitsize");
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return ~0;
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}
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}
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static inline type_t
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utype_src(nir_src src)
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{
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return utype_for_size(nir_src_bit_size(src));
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}
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static inline type_t
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utype_dst(nir_dest dst)
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{
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return utype_for_size(nir_dest_bit_size(dst));
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}
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/**
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* Convert nir bitsize to ir3 bitsize, handling the special case of 1b bools
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* which can be 16b or 32b depending on gen.
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*/
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static inline unsigned
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ir3_bitsize(struct ir3_context *ctx, unsigned nir_bitsize)
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{
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if (nir_bitsize == 1)
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return type_size(ctx->compiler->bool_type);
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return nir_bitsize;
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}
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#endif /* IR3_CONTEXT_H_ */
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