317 lines
10 KiB
C
317 lines
10 KiB
C
/*
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* Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#ifndef IR3_COMPILER_H_
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#define IR3_COMPILER_H_
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#include "compiler/nir/nir.h"
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#include "util/disk_cache.h"
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#include "util/log.h"
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#include "freedreno_dev_info.h"
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#include "ir3.h"
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struct ir3_ra_reg_set;
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struct ir3_shader;
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struct ir3_compiler {
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struct fd_device *dev;
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const struct fd_dev_id *dev_id;
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uint8_t gen;
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uint32_t shader_count;
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struct disk_cache *disk_cache;
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struct nir_shader_compiler_options nir_options;
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bool robust_buffer_access2;
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/*
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* Configuration options for things that are handled differently on
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* different generations:
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*/
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/* a4xx (and later) drops SP_FS_FLAT_SHAD_MODE_REG_* for flat-interpolate
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* so we need to use ldlv.u32 to load the varying directly:
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*/
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bool flat_bypass;
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/* on a3xx, we need to add one to # of array levels:
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*/
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bool levels_add_one;
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/* on a3xx, we need to scale up integer coords for isaml based
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* on LoD:
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*/
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bool unminify_coords;
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/* on a3xx do txf_ms w/ isaml and scaled coords: */
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bool txf_ms_with_isaml;
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/* on a4xx, for array textures we need to add 0.5 to the array
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* index coordinate:
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*/
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bool array_index_add_half;
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/* on a6xx, rewrite samgp to sequence of samgq0-3 in vertex shaders:
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*/
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bool samgq_workaround;
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/* on a650, vertex shader <-> tess control io uses LDL/STL */
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bool tess_use_shared;
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/* The maximum number of constants, in vec4's, across the entire graphics
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* pipeline.
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*/
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uint16_t max_const_pipeline;
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/* The maximum number of constants, in vec4's, for VS+HS+DS+GS. */
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uint16_t max_const_geom;
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/* The maximum number of constants, in vec4's, for FS. */
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uint16_t max_const_frag;
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/* A "safe" max constlen that can be applied to each shader in the
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* pipeline which we guarantee will never exceed any combined limits.
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*/
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uint16_t max_const_safe;
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/* The maximum number of constants, in vec4's, for compute shaders. */
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uint16_t max_const_compute;
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/* Number of instructions that the shader's base address and length
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* (instrlen divides instruction count by this) must be aligned to.
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*/
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uint32_t instr_align;
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/* on a3xx, the unit of indirect const load is higher than later gens (in
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* vec4 units):
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*/
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uint32_t const_upload_unit;
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/* The base number of threads per wave. Some stages may be able to double
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* this.
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*/
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uint32_t threadsize_base;
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/* On at least a6xx, waves are always launched in pairs. In calculations
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* about occupancy, we pretend that each wave pair is actually one wave,
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* which simplifies many of the calculations, but means we have to
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* multiply threadsize_base by this number.
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*/
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uint32_t wave_granularity;
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/* The maximum number of simultaneous waves per core. */
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uint32_t max_waves;
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/* This is theoretical maximum number of vec4 registers that one wave of
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* the base threadsize could use. To get the actual size of the register
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* file in bytes one would need to compute:
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*
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* reg_size_vec4 * threadsize_base * wave_granularity * 16 (bytes per vec4)
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*
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* However this number is more often what we actually need. For example, a
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* max_reg more than half of this will result in a doubled threadsize
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* being impossible (because double-sized waves take up twice as many
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* registers). Also, the formula for the occupancy given a particular
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* register footprint is simpler.
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*
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* It is in vec4 units because the register file is allocated
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* with vec4 granularity, so it's in the same units as max_reg.
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*/
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uint32_t reg_size_vec4;
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/* The size of local memory in bytes */
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uint32_t local_mem_size;
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/* The number of total branch stack entries, divided by wave_granularity. */
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uint32_t branchstack_size;
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/* Whether clip+cull distances are supported */
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bool has_clip_cull;
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/* Whether private memory is supported */
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bool has_pvtmem;
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/* True if 16-bit descriptors are used for both 16-bit and 32-bit access. */
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bool storage_16bit;
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/* True if getfiberid, getlast.w8, brcst.active, and quad_shuffle
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* instructions are supported which are necessary to support
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* subgroup quad and arithmetic operations.
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*/
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bool has_getfiberid;
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/* MAX_COMPUTE_VARIABLE_GROUP_INVOCATIONS_ARB */
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uint32_t max_variable_workgroup_size;
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bool has_dp2acc;
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bool has_dp4acc;
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/* Type to use for 1b nir bools: */
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type_t bool_type;
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/* Whether compute invocation params are passed in via shared regfile or
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* constbuf. a5xx+ has the shared regfile.
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*/
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bool has_shared_regfile;
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/* True if preamble instructions (shps, shpe, etc.) are supported */
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bool has_preamble;
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bool push_ubo_with_preamble;
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/* Where the shared consts start in constants file, in vec4's. */
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uint16_t shared_consts_base_offset;
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/* The size of shared consts for CS and FS(in vec4's).
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* Also the size that is actually used on geometry stages (on a6xx).
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*/
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uint64_t shared_consts_size;
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/* Found on a6xx for geometry stages, that is different from
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* actually used shared consts.
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*
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* TODO: Keep an eye on this for next gens.
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*/
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uint64_t geom_shared_consts_size_quirk;
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};
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struct ir3_compiler_options {
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/* If true, UBO/SSBO accesses are assumed to be bounds-checked as defined by
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* VK_EXT_robustness2 and optimizations may have to be more conservative.
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*/
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bool robust_buffer_access2;
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/* If true, promote UBOs (except for constant data) to constants using ldc.k
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* in the preamble. The driver should ignore everything in ubo_state except
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* for the constant data UBO, which is excluded because the command pushing
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* constants for it can be pre-baked when compiling the shader.
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*/
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bool push_ubo_with_preamble;
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/* If true, disable the shader cache. The driver is then responsible for
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* caching.
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*/
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bool disable_cache;
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};
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void ir3_compiler_destroy(struct ir3_compiler *compiler);
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struct ir3_compiler *ir3_compiler_create(struct fd_device *dev,
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const struct fd_dev_id *dev_id,
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const struct ir3_compiler_options *options);
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void ir3_disk_cache_init(struct ir3_compiler *compiler);
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void ir3_disk_cache_init_shader_key(struct ir3_compiler *compiler,
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struct ir3_shader *shader);
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struct ir3_shader_variant *ir3_retrieve_variant(struct blob_reader *blob,
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struct ir3_compiler *compiler,
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void *mem_ctx);
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void ir3_store_variant(struct blob *blob, struct ir3_shader_variant *v);
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bool ir3_disk_cache_retrieve(struct ir3_shader *shader,
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struct ir3_shader_variant *v);
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void ir3_disk_cache_store(struct ir3_shader *shader,
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struct ir3_shader_variant *v);
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const nir_shader_compiler_options *
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ir3_get_compiler_options(struct ir3_compiler *compiler);
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int ir3_compile_shader_nir(struct ir3_compiler *compiler,
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struct ir3_shader *shader,
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struct ir3_shader_variant *so);
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/* gpu pointer size in units of 32bit registers/slots */
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static inline unsigned
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ir3_pointer_size(struct ir3_compiler *compiler)
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{
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return fd_dev_64b(compiler->dev_id) ? 2 : 1;
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}
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enum ir3_shader_debug {
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IR3_DBG_SHADER_VS = BITFIELD_BIT(0),
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IR3_DBG_SHADER_TCS = BITFIELD_BIT(1),
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IR3_DBG_SHADER_TES = BITFIELD_BIT(2),
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IR3_DBG_SHADER_GS = BITFIELD_BIT(3),
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IR3_DBG_SHADER_FS = BITFIELD_BIT(4),
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IR3_DBG_SHADER_CS = BITFIELD_BIT(5),
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IR3_DBG_DISASM = BITFIELD_BIT(6),
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IR3_DBG_OPTMSGS = BITFIELD_BIT(7),
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IR3_DBG_FORCES2EN = BITFIELD_BIT(8),
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IR3_DBG_NOUBOOPT = BITFIELD_BIT(9),
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IR3_DBG_NOFP16 = BITFIELD_BIT(10),
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IR3_DBG_NOCACHE = BITFIELD_BIT(11),
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IR3_DBG_SPILLALL = BITFIELD_BIT(12),
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IR3_DBG_NOPREAMBLE = BITFIELD_BIT(13),
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/* DEBUG-only options: */
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IR3_DBG_SCHEDMSGS = BITFIELD_BIT(20),
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IR3_DBG_RAMSGS = BITFIELD_BIT(21),
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/* Only used for the disk-caching logic: */
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IR3_DBG_ROBUST_UBO_ACCESS = BITFIELD_BIT(30),
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};
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extern enum ir3_shader_debug ir3_shader_debug;
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extern const char *ir3_shader_override_path;
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static inline bool
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shader_debug_enabled(gl_shader_stage type)
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{
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if (ir3_shader_debug & IR3_DBG_DISASM)
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return true;
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switch (type) {
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case MESA_SHADER_VERTEX:
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return !!(ir3_shader_debug & IR3_DBG_SHADER_VS);
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case MESA_SHADER_TESS_CTRL:
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return !!(ir3_shader_debug & IR3_DBG_SHADER_TCS);
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case MESA_SHADER_TESS_EVAL:
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return !!(ir3_shader_debug & IR3_DBG_SHADER_TES);
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case MESA_SHADER_GEOMETRY:
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return !!(ir3_shader_debug & IR3_DBG_SHADER_GS);
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case MESA_SHADER_FRAGMENT:
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return !!(ir3_shader_debug & IR3_DBG_SHADER_FS);
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case MESA_SHADER_COMPUTE:
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case MESA_SHADER_KERNEL:
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return !!(ir3_shader_debug & IR3_DBG_SHADER_CS);
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default:
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assert(0);
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return false;
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}
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}
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static inline void
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ir3_debug_print(struct ir3 *ir, const char *when)
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{
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if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
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mesa_logi("%s:", when);
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ir3_print(ir);
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}
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}
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#endif /* IR3_COMPILER_H_ */
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