445 lines
16 KiB
C
445 lines
16 KiB
C
/*
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* Copyright (C) 2017-2018 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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/* 500 gets us LDIB but doesn't change any other a4xx instructions */
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#define GPU 500
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#include "ir3_context.h"
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#include "ir3_image.h"
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/* SSBO data is available at this CB address, addressed like regular consts
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* containing the following data in each vec4:
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*
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* [ base address, pitch, array_pitch, cpp ]
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*
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* These mirror the values uploaded to A4XX_SSBO_0 state. For A5XX, these are
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* uploaded manually by the driver.
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*/
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#define A4XX_SSBO_CB_BASE(i) (0x700 + ((i) << 2))
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/*
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* Handlers for instructions changed/added in a4xx:
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*/
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/* Convert byte offset to address of appropriate width for GPU */
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static struct ir3_instruction *
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byte_offset_to_address(struct ir3_context *ctx,
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nir_src *ssbo,
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struct ir3_instruction *byte_offset)
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{
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struct ir3_block *b = ctx->block;
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if (ctx->compiler->gen == 4) {
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uint32_t index = nir_src_as_uint(*ssbo);
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unsigned cb = A4XX_SSBO_CB_BASE(index);
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byte_offset = ir3_ADD_U(b, create_uniform(b, cb), 0, byte_offset, 0);
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}
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if (fd_dev_64b(ctx->compiler->dev_id)) {
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return ir3_collect(b, byte_offset, create_immed(b, 0));
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} else {
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return byte_offset;
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}
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}
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/* src[] = { buffer_index, offset }. No const_index */
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static void
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emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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struct ir3_instruction **dst)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *ldgb, *src0, *src1, *byte_offset, *offset;
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struct ir3_instruction *ssbo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
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byte_offset = ir3_get_src(ctx, &intr->src[1])[0];
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offset = ir3_get_src(ctx, &intr->src[2])[0];
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/* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
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src0 = byte_offset_to_address(ctx, &intr->src[0], byte_offset);
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src1 = offset;
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ldgb = ir3_LDGB(b, ssbo, 0, src0, 0, src1, 0);
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ldgb->dsts[0]->wrmask = MASK(intr->num_components);
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ldgb->cat6.iim_val = intr->num_components;
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ldgb->cat6.d = 4;
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ldgb->cat6.type = TYPE_U32;
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ldgb->barrier_class = IR3_BARRIER_BUFFER_R;
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ldgb->barrier_conflict = IR3_BARRIER_BUFFER_W;
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ir3_split_dest(b, dst, ldgb, 0, intr->num_components);
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}
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/* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
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static void
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emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *stgb, *src0, *src1, *src2, *byte_offset, *offset;
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unsigned wrmask = nir_intrinsic_write_mask(intr);
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unsigned ncomp = ffs(~wrmask) - 1;
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assert(wrmask == BITFIELD_MASK(intr->num_components));
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struct ir3_instruction *ssbo = ir3_ssbo_to_ibo(ctx, intr->src[1]);
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byte_offset = ir3_get_src(ctx, &intr->src[2])[0];
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offset = ir3_get_src(ctx, &intr->src[3])[0];
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/* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
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* nir already *= 4:
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*/
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src0 = ir3_create_collect(b, ir3_get_src(ctx, &intr->src[0]), ncomp);
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src1 = offset;
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src2 = byte_offset_to_address(ctx, &intr->src[1], byte_offset);
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stgb = ir3_STGB(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
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stgb->cat6.iim_val = ncomp;
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stgb->cat6.d = 4;
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stgb->cat6.type = TYPE_U32;
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stgb->barrier_class = IR3_BARRIER_BUFFER_W;
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stgb->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
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array_insert(b, b->keeps, stgb);
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}
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/*
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* SSBO atomic intrinsics
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*
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* All of the SSBO atomic memory operations read a value from memory,
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* compute a new value using one of the operations below, write the new
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* value to memory, and return the original value read.
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*
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* All operations take 3 sources except CompSwap that takes 4. These
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* sources represent:
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*
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* 0: The SSBO buffer index.
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* 1: The byte offset into the SSBO buffer of the variable that the atomic
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* operation will operate on.
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* 2: The data parameter to the atomic function (i.e. the value to add
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* in ssbo_atomic_add, etc).
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* 3: CompSwap: the second data parameter.
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* Non-CompSwap: The dword offset into the SSBO buffer variable.
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* 4: CompSwap: The dword offset into the SSBO buffer variable.
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*
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* We use custom ssbo_*_ir3 intrinsics generated by ir3_nir_lower_io_offsets()
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* so we can have the dword offset generated in NIR.
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*/
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static struct ir3_instruction *
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emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *atomic;
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type_t type = TYPE_U32;
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struct ir3_instruction *ssbo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
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struct ir3_instruction *data = ir3_get_src(ctx, &intr->src[2])[0];
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/* 64b byte offset */
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struct ir3_instruction *byte_offset =
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byte_offset_to_address(ctx, &intr->src[0], ir3_get_src(ctx, &intr->src[1])[0]);
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/* dword offset for everything but comp_swap */
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struct ir3_instruction *src3 = ir3_get_src(ctx, &intr->src[3])[0];
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switch (intr->intrinsic) {
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case nir_intrinsic_ssbo_atomic_add_ir3:
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atomic = ir3_ATOMIC_S_ADD(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
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break;
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case nir_intrinsic_ssbo_atomic_imin_ir3:
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atomic = ir3_ATOMIC_S_MIN(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
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type = TYPE_S32;
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break;
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case nir_intrinsic_ssbo_atomic_umin_ir3:
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atomic = ir3_ATOMIC_S_MIN(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
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break;
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case nir_intrinsic_ssbo_atomic_imax_ir3:
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atomic = ir3_ATOMIC_S_MAX(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
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type = TYPE_S32;
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break;
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case nir_intrinsic_ssbo_atomic_umax_ir3:
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atomic = ir3_ATOMIC_S_MAX(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
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break;
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case nir_intrinsic_ssbo_atomic_and_ir3:
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atomic = ir3_ATOMIC_S_AND(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
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break;
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case nir_intrinsic_ssbo_atomic_or_ir3:
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atomic = ir3_ATOMIC_S_OR(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
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break;
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case nir_intrinsic_ssbo_atomic_xor_ir3:
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atomic = ir3_ATOMIC_S_XOR(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
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break;
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case nir_intrinsic_ssbo_atomic_exchange_ir3:
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atomic = ir3_ATOMIC_S_XCHG(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
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break;
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case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
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/* for cmpxchg, src0 is [ui]vec2(data, compare): */
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data = ir3_collect(b, src3, data);
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struct ir3_instruction *dword_offset = ir3_get_src(ctx, &intr->src[4])[0];
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atomic = ir3_ATOMIC_S_CMPXCHG(b, ssbo, 0, data, 0, dword_offset, 0,
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byte_offset, 0);
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break;
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default:
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unreachable("boo");
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}
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atomic->cat6.iim_val = 1;
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atomic->cat6.d = 4;
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atomic->cat6.type = type;
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atomic->barrier_class = IR3_BARRIER_BUFFER_W;
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atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
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/* even if nothing consume the result, we can't DCE the instruction: */
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array_insert(b, b->keeps, atomic);
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return atomic;
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}
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static struct ir3_instruction *
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get_image_offset(struct ir3_context *ctx, const nir_intrinsic_instr *instr,
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struct ir3_instruction *const *coords, bool byteoff)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *offset;
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unsigned index = nir_src_as_uint(instr->src[0]);
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unsigned ncoords = ir3_get_image_coords(instr, NULL);
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/* to calculate the byte offset (yes, uggg) we need (up to) three
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* const values to know the bytes per pixel, and y and z stride:
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*/
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unsigned cb;
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if (ctx->compiler->gen > 4) {
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const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
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assert(const_state->image_dims.mask & (1 << index));
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cb = regid(const_state->offsets.image_dims, 0) +
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const_state->image_dims.off[index];
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} else {
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index += ctx->s->info.num_ssbos;
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cb = A4XX_SSBO_CB_BASE(index);
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}
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/* offset = coords.x * bytes_per_pixel: */
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if (ctx->compiler->gen == 4)
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offset = ir3_MUL_S24(b, coords[0], 0, create_uniform(b, cb + 3), 0);
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else
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offset = ir3_MUL_S24(b, coords[0], 0, create_uniform(b, cb + 0), 0);
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if (ncoords > 1) {
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/* offset += coords.y * y_pitch: */
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offset =
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ir3_MAD_S24(b, create_uniform(b, cb + 1), 0, coords[1], 0, offset, 0);
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}
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if (ncoords > 2) {
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/* offset += coords.z * z_pitch: */
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offset =
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ir3_MAD_S24(b, create_uniform(b, cb + 2), 0, coords[2], 0, offset, 0);
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}
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/* a4xx: must add in the base address: */
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if (ctx->compiler->gen == 4)
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offset = ir3_ADD_U(b, offset, 0, create_uniform(b, cb + 0), 0);
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if (!byteoff) {
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/* Some cases, like atomics, seem to use dword offset instead
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* of byte offsets.. blob just puts an extra shr.b in there
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* in those cases:
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*/
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offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
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}
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if (fd_dev_64b(ctx->compiler->dev_id))
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return ir3_collect(b, offset, create_immed(b, 0));
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else
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return offset;
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}
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/* src[] = { deref, coord, sample_index }. const_index[] = {} */
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static void
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emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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struct ir3_instruction **dst)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *const *coords = ir3_get_src(ctx, &intr->src[1]);
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struct ir3_instruction *ibo = ir3_image_to_ibo(ctx, intr->src[0]);
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struct ir3_instruction *offset = get_image_offset(ctx, intr, coords, true);
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unsigned ncoords = ir3_get_image_coords(intr, NULL);
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unsigned ncomp =
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ir3_get_num_components_for_image_format(nir_intrinsic_format(intr));
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struct ir3_instruction *ldib;
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/* At least A420 does not have LDIB. Use LDGB and perform conversion
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* ourselves.
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*
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* TODO: Actually do the conversion. ES 3.1 only requires this for
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* single-component 32-bit types anyways.
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*/
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if (ctx->compiler->gen > 4) {
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ldib = ir3_LDIB(
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b, ibo, 0, offset, 0, ir3_create_collect(b, coords, ncoords), 0);
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} else {
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ldib = ir3_LDGB(
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b, ibo, 0, offset, 0, ir3_create_collect(b, coords, ncoords), 0);
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switch (nir_intrinsic_format(intr)) {
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case PIPE_FORMAT_R32_UINT:
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case PIPE_FORMAT_R32_SINT:
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case PIPE_FORMAT_R32_FLOAT:
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break;
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default:
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/* For some reason even more 32-bit components don't work. */
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assert(0);
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break;
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}
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}
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ldib->dsts[0]->wrmask = MASK(intr->num_components);
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ldib->cat6.iim_val = ncomp;
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ldib->cat6.d = ncoords;
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ldib->cat6.type = ir3_get_type_for_image_intrinsic(intr);
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ldib->cat6.typed = true;
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ldib->barrier_class = IR3_BARRIER_IMAGE_R;
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ldib->barrier_conflict = IR3_BARRIER_IMAGE_W;
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ir3_split_dest(b, dst, ldib, 0, intr->num_components);
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}
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/* src[] = { index, coord, sample_index, value }. const_index[] = {} */
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static void
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emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *stib, *offset;
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struct ir3_instruction *const *value = ir3_get_src(ctx, &intr->src[3]);
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struct ir3_instruction *const *coords = ir3_get_src(ctx, &intr->src[1]);
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struct ir3_instruction *ibo = ir3_image_to_ibo(ctx, intr->src[0]);
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unsigned ncoords = ir3_get_image_coords(intr, NULL);
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unsigned ncomp =
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ir3_get_num_components_for_image_format(nir_intrinsic_format(intr));
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/* src0 is value
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* src1 is coords
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* src2 is 64b byte offset
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*/
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offset = get_image_offset(ctx, intr, coords, true);
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/* NOTE: stib seems to take byte offset, but stgb.typed can be used
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* too and takes a dword offset.. not quite sure yet why blob uses
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* one over the other in various cases.
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*/
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stib = ir3_STIB(b, ibo, 0, ir3_create_collect(b, value, ncomp), 0,
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ir3_create_collect(b, coords, ncoords), 0, offset, 0);
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stib->cat6.iim_val = ncomp;
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stib->cat6.d = ncoords;
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stib->cat6.type = ir3_get_type_for_image_intrinsic(intr);
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stib->cat6.typed = true;
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stib->barrier_class = IR3_BARRIER_IMAGE_W;
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stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
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array_insert(b, b->keeps, stib);
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}
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/* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
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static struct ir3_instruction *
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emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *atomic, *src0, *src1, *src2;
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struct ir3_instruction *const *coords = ir3_get_src(ctx, &intr->src[1]);
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struct ir3_instruction *image = ir3_image_to_ibo(ctx, intr->src[0]);
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unsigned ncoords = ir3_get_image_coords(intr, NULL);
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/* src0 is value (or uvec2(value, compare))
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* src1 is coords
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* src2 is 64b byte offset
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*/
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src0 = ir3_get_src(ctx, &intr->src[3])[0];
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src1 = ir3_create_collect(b, coords, ncoords);
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src2 = get_image_offset(ctx, intr, coords, ctx->compiler->gen == 4);
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switch (intr->intrinsic) {
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case nir_intrinsic_image_atomic_add:
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atomic = ir3_ATOMIC_S_ADD(b, image, 0, src0, 0, src1, 0, src2, 0);
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break;
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case nir_intrinsic_image_atomic_imin:
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case nir_intrinsic_image_atomic_umin:
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atomic = ir3_ATOMIC_S_MIN(b, image, 0, src0, 0, src1, 0, src2, 0);
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break;
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case nir_intrinsic_image_atomic_imax:
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case nir_intrinsic_image_atomic_umax:
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atomic = ir3_ATOMIC_S_MAX(b, image, 0, src0, 0, src1, 0, src2, 0);
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break;
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case nir_intrinsic_image_atomic_and:
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atomic = ir3_ATOMIC_S_AND(b, image, 0, src0, 0, src1, 0, src2, 0);
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break;
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case nir_intrinsic_image_atomic_or:
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atomic = ir3_ATOMIC_S_OR(b, image, 0, src0, 0, src1, 0, src2, 0);
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break;
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case nir_intrinsic_image_atomic_xor:
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atomic = ir3_ATOMIC_S_XOR(b, image, 0, src0, 0, src1, 0, src2, 0);
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break;
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case nir_intrinsic_image_atomic_exchange:
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atomic = ir3_ATOMIC_S_XCHG(b, image, 0, src0, 0, src1, 0, src2, 0);
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break;
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case nir_intrinsic_image_atomic_comp_swap:
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/* for cmpxchg, src0 is [ui]vec2(data, compare): */
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src0 = ir3_collect(b, ir3_get_src(ctx, &intr->src[4])[0], src0);
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atomic = ir3_ATOMIC_S_CMPXCHG(b, image, 0, src0, 0, src1, 0, src2, 0);
|
|
break;
|
|
default:
|
|
unreachable("boo");
|
|
}
|
|
|
|
atomic->cat6.iim_val = 1;
|
|
atomic->cat6.d = ncoords;
|
|
atomic->cat6.type = ir3_get_type_for_image_intrinsic(intr);
|
|
atomic->cat6.typed = ctx->compiler->gen == 5;
|
|
atomic->barrier_class = IR3_BARRIER_IMAGE_W;
|
|
atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
|
|
|
|
/* even if nothing consume the result, we can't DCE the instruction: */
|
|
array_insert(b, b->keeps, atomic);
|
|
|
|
return atomic;
|
|
}
|
|
|
|
static struct ir3_instruction *
|
|
emit_intrinsic_atomic_global(struct ir3_context *ctx, nir_intrinsic_instr *intr)
|
|
{
|
|
unreachable("Global atomic are unimplemented on A5xx");
|
|
}
|
|
|
|
const struct ir3_context_funcs ir3_a4xx_funcs = {
|
|
.emit_intrinsic_load_ssbo = emit_intrinsic_load_ssbo,
|
|
.emit_intrinsic_store_ssbo = emit_intrinsic_store_ssbo,
|
|
.emit_intrinsic_atomic_ssbo = emit_intrinsic_atomic_ssbo,
|
|
.emit_intrinsic_load_image = emit_intrinsic_load_image,
|
|
.emit_intrinsic_store_image = emit_intrinsic_store_image,
|
|
.emit_intrinsic_atomic_image = emit_intrinsic_atomic_image,
|
|
.emit_intrinsic_image_size = emit_intrinsic_image_size_tex,
|
|
.emit_intrinsic_load_global_ir3 = NULL,
|
|
.emit_intrinsic_store_global_ir3 = NULL,
|
|
.emit_intrinsic_atomic_global = emit_intrinsic_atomic_global,
|
|
};
|