350 lines
12 KiB
C
350 lines
12 KiB
C
/*
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* Copyright © 2021 Ilia Mirkin
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "ir3/ir3_compiler.h"
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#include "util/u_math.h"
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#include "util/u_queue.h"
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#include "util/half_float.h"
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#include "adreno_pm4.xml.h"
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#include "adreno_common.xml.h"
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#include "a4xx.xml.h"
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#include "ir3_asm.h"
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#include "main.h"
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struct a4xx_backend {
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struct backend base;
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struct ir3_compiler *compiler;
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struct fd_device *dev;
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};
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define_cast(backend, a4xx_backend);
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/*
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* Backend implementation:
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*/
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static struct kernel *
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a4xx_assemble(struct backend *b, FILE *in)
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{
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struct a4xx_backend *a4xx_backend = to_a4xx_backend(b);
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struct ir3_kernel *ir3_kernel = ir3_asm_assemble(a4xx_backend->compiler, in);
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ir3_kernel->backend = b;
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return &ir3_kernel->base;
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}
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static void
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a4xx_disassemble(struct kernel *kernel, FILE *out)
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{
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ir3_asm_disassemble(to_ir3_kernel(kernel), out);
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}
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static void
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cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
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{
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struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
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struct ir3_shader_variant *v = ir3_kernel->v;
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const struct ir3_info *i = &v->info;
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enum a3xx_threadsize thrsz = i->double_threadsize ? FOUR_QUADS : TWO_QUADS;
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OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000012);
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OUT_WFI(ring);
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OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
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OUT_RING(ring, 0x0000001e);
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OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
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OUT_RING(ring, 0x00000038);
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OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
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OUT_RING(ring, 0x00000000);
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OUT_WFI(ring);
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OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
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OUT_RING(ring, 0x00000003);
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OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 1);
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OUT_RING(ring, 0x080005f0);
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OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
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OUT_RING(ring, 0x00000038);
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OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
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OUT_RING(ring, 0x00860010);
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// OUT_RING(ring, 0x00920000);
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OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
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OUT_RING(ring, 0x000004ff);
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// OUT_RING(ring, 0x00000260);
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OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG1, 1);
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OUT_RING(ring, 0x80000000);
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OUT_PKT0(ring, REG_A4XX_SP_CS_CTRL_REG0, 1);
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OUT_RING(ring,
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A4XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
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A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE |
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A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
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A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1));
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OUT_PKT0(ring, REG_A4XX_HLSQ_CS_CONTROL_REG, 1);
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OUT_RING(ring, A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(0) |
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A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(0) |
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A4XX_HLSQ_CS_CONTROL_REG_ENABLED |
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A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(1) |
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COND(v->has_ssbo, A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE) |
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A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(v->constlen / 4));
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OUT_PKT0(ring, REG_A4XX_SP_CS_OBJ_START, 1);
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OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START */
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OUT_PKT0(ring, REG_A4XX_SP_CS_LENGTH_REG, 1);
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OUT_RING(ring, v->instrlen);
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uint32_t local_invocation_id, work_group_id, num_wg_id;
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local_invocation_id =
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ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
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work_group_id = ir3_kernel->info.wgid;
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num_wg_id = ir3_kernel->info.numwg;
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OUT_PKT0(ring, REG_A4XX_HLSQ_CL_CONTROL_0, 2);
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OUT_RING(ring, A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(work_group_id) |
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A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(regid(63, 0)) |
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A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(local_invocation_id));
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OUT_RING(ring, A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(regid(63, 0)) |
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A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(regid(63, 0)));
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OUT_PKT0(ring, REG_A4XX_HLSQ_CL_KERNEL_CONST, 1);
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OUT_RING(ring, A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(regid(63, 0)) |
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A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(num_wg_id));
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OUT_PKT0(ring, REG_A4XX_HLSQ_CL_WG_OFFSET, 1);
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OUT_RING(ring, A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(regid(63, 0)));
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OUT_PKT3(ring, CP_LOAD_STATE4, 2);
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OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
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CP_LOAD_STATE4_0_STATE_SRC(SS4_INDIRECT) |
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CP_LOAD_STATE4_0_STATE_BLOCK(SB4_CS_SHADER) |
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CP_LOAD_STATE4_0_NUM_UNIT(v->instrlen));
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OUT_RELOC(ring, v->bo, 0, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
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}
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static void
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emit_const(struct fd_ringbuffer *ring, struct kernel *kernel, uint32_t constid, uint32_t sizedwords,
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const uint32_t *dwords)
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{
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uint32_t align_sz;
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assert((constid % 4) == 0);
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/* Overwrite appropriate entries with buffer addresses */
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struct fd_bo **replacements = calloc(sizedwords, sizeof(struct fd_bo *));
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for (int i = 0; i < MAX_BUFS; i++) {
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if (kernel->buf_addr_regs[i] != INVALID_REG) {
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int idx = kernel->buf_addr_regs[i];
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assert(idx < sizedwords);
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replacements[idx] = kernel->bufs[i];
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}
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}
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align_sz = align(sizedwords, 4);
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OUT_PKT3(ring, CP_LOAD_STATE4, 2 + align_sz);
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OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(constid / 4) |
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CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
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CP_LOAD_STATE4_0_STATE_BLOCK(SB4_CS_SHADER) |
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CP_LOAD_STATE4_0_NUM_UNIT(DIV_ROUND_UP(sizedwords, 4)));
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OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
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CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
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for (unsigned i = 0; i < sizedwords; i++) {
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if (replacements[i])
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OUT_RELOC(ring, replacements[i], 0, 0, 0);
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else
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OUT_RING(ring, dwords[i]);
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}
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/* Zero-pad to multiple of 4 dwords */
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for (uint32_t i = sizedwords; i < align_sz; i++) {
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OUT_RING(ring, 0);
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}
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free(replacements);
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}
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static void
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cs_const_emit(struct fd_ringbuffer *ring, struct kernel *kernel,
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uint32_t grid[3])
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{
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struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
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struct ir3_shader_variant *v = ir3_kernel->v;
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const struct ir3_const_state *const_state = ir3_const_state(v);
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uint32_t base = const_state->offsets.immediate;
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int size = DIV_ROUND_UP(const_state->immediates_count, 4);
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/* truncate size to avoid writing constants that shader
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* does not use:
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*/
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size = MIN2(size + base, v->constlen) - base;
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/* convert out of vec4: */
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base *= 4;
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size *= 4;
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if (size > 0) {
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emit_const(ring, kernel, base, size, const_state->immediates);
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}
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}
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static void
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cs_ibo_emit(struct fd_ringbuffer *ring, struct fd_submit *submit,
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struct kernel *kernel)
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{
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OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (4 * kernel->num_bufs));
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OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
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CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
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CP_LOAD_STATE4_0_STATE_BLOCK(SB4_CS_SSBO) |
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CP_LOAD_STATE4_0_NUM_UNIT(kernel->num_bufs));
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OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
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CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
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for (unsigned i = 0; i < kernel->num_bufs; i++) {
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OUT_RELOC(ring, kernel->bufs[i], 0, 0, 0);
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#if 1
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OUT_RING(ring, 0);
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OUT_RING(ring, 0);
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OUT_RING(ring, 0);
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#else
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OUT_RING(ring, kernel->buf_sizes[i]);
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OUT_RING(ring, kernel->buf_sizes[i]);
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OUT_RING(ring, 0x00000004);
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#endif
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}
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OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * kernel->num_bufs));
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OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
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CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
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CP_LOAD_STATE4_0_STATE_BLOCK(SB4_CS_SSBO) |
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CP_LOAD_STATE4_0_NUM_UNIT(kernel->num_bufs));
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OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
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CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
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for (unsigned i = 0; i < kernel->num_bufs; i++) {
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unsigned sz = kernel->buf_sizes[i];
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/* width is in dwords, overflows into height: */
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sz /= 4;
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#if 1
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OUT_RING(ring, A4XX_SSBO_1_0_WIDTH(sz));
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OUT_RING(ring, A4XX_SSBO_1_1_HEIGHT(sz >> 16));
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#else
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OUT_RING(ring, A4XX_SSBO_1_0_WIDTH(sz) |
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A4XX_SSBO_1_0_FMT(RB4_R32_UINT) |
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A4XX_SSBO_1_0_CPP(4));
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OUT_RING(ring, A4XX_SSBO_1_1_HEIGHT(DIV_ROUND_UP(sz, 1 << 16)) |
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A4XX_SSBO_1_1_DEPTH(1));
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#endif
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}
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}
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static void
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a4xx_emit_grid(struct kernel *kernel, uint32_t grid[3],
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struct fd_submit *submit)
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{
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struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
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submit, 0, FD_RINGBUFFER_PRIMARY | FD_RINGBUFFER_GROWABLE);
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cs_program_emit(ring, kernel);
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cs_const_emit(ring, kernel, grid);
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cs_ibo_emit(ring, submit, kernel);
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const unsigned *local_size = kernel->local_size;
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const unsigned *num_groups = grid;
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unsigned work_dim = 0;
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for (int i = 0; i < 3; i++) {
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if (!grid[i])
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break;
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work_dim++;
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}
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OUT_PKT0(ring, REG_A4XX_HLSQ_CL_NDRANGE_0, 7);
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OUT_RING(ring, A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(work_dim) |
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A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
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A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
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A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
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OUT_RING(ring,
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A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(local_size[0] * num_groups[0]));
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OUT_RING(ring, 0); /* HLSQ_CL_NDRANGE_2_GLOBALOFF_X */
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OUT_RING(ring,
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A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(local_size[1] * num_groups[1]));
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OUT_RING(ring, 0); /* HLSQ_CL_NDRANGE_4_GLOBALOFF_Y */
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OUT_RING(ring,
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A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(local_size[2] * num_groups[2]));
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OUT_RING(ring, 0); /* HLSQ_CL_NDRANGE_6_GLOBALOFF_Z */
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#if 1
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OUT_PKT3(ring, CP_EXEC_CS, 4);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(grid[0]));
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OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(grid[1]));
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OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(grid[2]));
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#else
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OUT_PKT0(ring, REG_A4XX_HLSQ_CL_KERNEL_GROUP_X, 3);
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OUT_RING(ring, grid[0]); /* HLSQ_CL_KERNEL_GROUP_X */
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OUT_RING(ring, grid[1]); /* HLSQ_CL_KERNEL_GROUP_Y */
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OUT_RING(ring, grid[2]); /* HLSQ_CL_KERNEL_GROUP_Z */
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OUT_PKT3(ring, CP_RUN_OPENCL, 1);
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OUT_RING(ring, 0);
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#endif
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OUT_WFI(ring);
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/* TODO: cache_flush */
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}
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struct backend *
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a4xx_init(struct fd_device *dev, const struct fd_dev_id *dev_id)
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{
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struct a4xx_backend *a4xx_backend = calloc(1, sizeof(*a4xx_backend));
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a4xx_backend->base = (struct backend){
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.assemble = a4xx_assemble,
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.disassemble = a4xx_disassemble,
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.emit_grid = a4xx_emit_grid,
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};
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a4xx_backend->compiler = ir3_compiler_create(dev, dev_id,
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&(struct ir3_compiler_options) {});
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a4xx_backend->dev = dev;
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return &a4xx_backend->base;
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}
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