212 lines
6.9 KiB
C
212 lines
6.9 KiB
C
/*
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* Copyright © 2020 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef FREEDRENO_DEVICE_INFO_H
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#define FREEDRENO_DEVICE_INFO_H
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Freedreno hardware description and quirks
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*/
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struct fd_dev_info {
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/* alignment for size of tiles */
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uint32_t tile_align_w, tile_align_h;
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/* gmem load/store granularity */
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uint32_t gmem_align_w, gmem_align_h;
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/* max tile size */
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uint32_t tile_max_w, tile_max_h;
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uint32_t num_vsc_pipes;
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/* number of CCU is always equal to the number of SP */
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union {
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uint32_t num_sp_cores;
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uint32_t num_ccu;
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};
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union {
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struct {
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/* Information for private memory calculations */
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uint32_t fibers_per_sp;
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uint32_t reg_size_vec4;
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/* The size (in instrlen units (128 bytes)) of instruction cache where
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* we preload a shader. Loading more than this could trigger a hang
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* on gen3 and later.
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*/
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uint32_t instr_cache_size;
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/* Whether the PC_MULTIVIEW_MASK register exists. */
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bool supports_multiview_mask;
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/* info for setting RB_CCU_CNTL */
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bool concurrent_resolve;
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bool has_z24uint_s8uint;
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bool tess_use_shared;
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/* Does the hw support GL_QCOM_shading_rate? */
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bool has_shading_rate;
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/* newer a6xx allows using 16-bit descriptor for both 16-bit
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* and 32-bit access
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*/
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bool storage_16bit;
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/* The latest known a630_sqe.fw fails to wait for WFI before
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* reading the indirect buffer when using CP_DRAW_INDIRECT_MULTI,
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* so we have to fall back to CP_WAIT_FOR_ME except for a650
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* which has a fixed firmware.
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*
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* TODO: There may be newer a630_sqe.fw released in the future
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* which fixes this, if so we should detect it and avoid this
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* workaround. Once we have uapi to query fw version, we can
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* replace this with minimum fw version.
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*/
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bool indirect_draw_wfm_quirk;
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/* On some GPUs, the depth test needs to be enabled when the
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* depth bounds test is enabled and the depth attachment uses UBWC.
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*/
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bool depth_bounds_require_depth_test_quirk;
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bool has_tex_filter_cubic;
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bool has_sample_locations;
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/* The firmware on newer a6xx drops CP_REG_WRITE support as we
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* can now use direct register writes for these regs.
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*/
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bool has_cp_reg_write;
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bool has_8bpp_ubwc;
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/* a650 seems to be affected by a bug where flushing CCU color into
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* depth or vice-versa requires a WFI. In particular, clearing a
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* depth attachment (which writes to it as a color attachment) then
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* using it as a normal depth attachment requires a WFI in addition
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* to the expected CCU_FLUSH_COLOR + CCU_INVALIDATE_DEPTH, even
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* though all those operations happen in the same stage. As this is
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* usually the only scenario where a CCU flush doesn't require a WFI
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* we just insert a WFI after every CCU flush.
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*
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* Tests affected include
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* dEQP-VK.renderpass.suballocation.formats.d16_unorm.* in sysmem
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* mode (a few tests flake when the entire series is run).
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*/
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bool has_ccu_flush_bug;
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bool has_lpac;
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bool has_getfiberid;
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bool has_dp2acc;
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bool has_dp4acc;
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/* LRZ fast-clear works on all gens, however blob disables it on
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* gen1 and gen2. We also elect to disable fast-clear on these gens
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* because for close to none gains it adds complexity and seem to work
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* a bit differently from gen3+. Which creates at least one edge case:
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* if first draw which uses LRZ fast-clear doesn't lock LRZ direction
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* the fast-clear value is undefined. For details see
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* https://gitlab.freedesktop.org/mesa/mesa/-/issues/6829
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*/
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bool enable_lrz_fast_clear;
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bool has_lrz_dir_tracking;
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bool lrz_track_quirk;
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struct {
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uint32_t RB_UNKNOWN_8E04_blit;
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uint32_t PC_POWER_CNTL;
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uint32_t TPL1_DBG_ECO_CNTL;
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} magic;
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} a6xx;
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};
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};
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struct fd_dev_id {
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uint32_t gpu_id;
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uint64_t chip_id;
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};
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/**
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* Note that gpu-id should be considered deprecated. For newer a6xx, if
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* there is no gpu-id, this attempts to generate one from the chip-id.
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* But that may not work forever, so avoid depending on this for newer
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* gens
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*/
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static inline uint32_t
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fd_dev_gpu_id(const struct fd_dev_id *id)
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{
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assert(id->gpu_id || id->chip_id);
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if (!id->gpu_id) {
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return ((id->chip_id >> 24) & 0xff) * 100 +
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((id->chip_id >> 16) & 0xff) * 10 +
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((id->chip_id >> 8) & 0xff);
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}
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return id->gpu_id;
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}
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static uint8_t
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fd_dev_gen(const struct fd_dev_id *id)
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{
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return fd_dev_gpu_id(id) / 100;
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}
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static inline bool
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fd_dev_64b(const struct fd_dev_id *id)
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{
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return fd_dev_gen(id) >= 5;
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}
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/* per CCU GMEM amount reserved for depth cache for direct rendering */
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#define A6XX_CCU_DEPTH_SIZE (64 * 1024)
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/* per CCU GMEM amount reserved for color cache used by GMEM resolves
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* which require color cache (non-BLIT event case).
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* this is smaller than what is normally used by direct rendering
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* (RB_CCU_CNTL.GMEM bit enables this smaller size)
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* if a GMEM resolve requires color cache, the driver needs to make sure
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* it will not overwrite pixel data in GMEM that is still needed
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*/
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#define A6XX_CCU_GMEM_COLOR_SIZE (16 * 1024)
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const struct fd_dev_info * fd_dev_info(const struct fd_dev_id *id);
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const char * fd_dev_name(const struct fd_dev_id *id);
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#ifdef __cplusplus
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} /* end of extern "C" */
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#endif
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#endif /* FREEDRENO_DEVICE_INFO_H */
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