372 lines
10 KiB
C
372 lines
10 KiB
C
/*
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* Copyright © 2021 Google, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <assert.h>
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#include <ctype.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "emu.h"
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#include "util.h"
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/*
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* Emulator Registers:
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*
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* Handles access to GPR, GPU, control, and pipe registers.
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*/
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static bool
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is_draw_state_control_reg(unsigned n)
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{
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char *reg_name = afuc_control_reg_name(n);
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if (!reg_name)
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return false;
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bool ret = !!strstr(reg_name, "DRAW_STATE");
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free(reg_name);
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return ret;
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}
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uint32_t
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emu_get_control_reg(struct emu *emu, unsigned n)
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{
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assert(n < ARRAY_SIZE(emu->control_regs.val));
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if (is_draw_state_control_reg(n))
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return emu_get_draw_state_reg(emu, n);
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return emu->control_regs.val[n];
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}
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void
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emu_set_control_reg(struct emu *emu, unsigned n, uint32_t val)
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{
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EMU_CONTROL_REG(PACKET_TABLE_WRITE);
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EMU_CONTROL_REG(PACKET_TABLE_WRITE_ADDR);
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EMU_CONTROL_REG(REG_WRITE);
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EMU_CONTROL_REG(REG_WRITE_ADDR);
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assert(n < ARRAY_SIZE(emu->control_regs.val));
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BITSET_SET(emu->control_regs.written, n);
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emu->control_regs.val[n] = val;
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/* Some control regs have special action on write: */
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if (n == emu_reg_offset(&PACKET_TABLE_WRITE)) {
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unsigned write_addr = emu_get_reg32(emu, &PACKET_TABLE_WRITE_ADDR);
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assert(write_addr < ARRAY_SIZE(emu->jmptbl));
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emu->jmptbl[write_addr] = val;
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emu_set_reg32(emu, &PACKET_TABLE_WRITE_ADDR, write_addr + 1);
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} else if (n == emu_reg_offset(®_WRITE)) {
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uint32_t write_addr = emu_get_reg32(emu, ®_WRITE_ADDR);
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/* Upper bits seem like some flags, not part of the actual
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* register offset.. not sure what they mean yet:
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*/
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uint32_t flags = write_addr >> 16;
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write_addr &= 0xffff;
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emu_set_gpu_reg(emu, write_addr++, val);
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emu_set_reg32(emu, ®_WRITE_ADDR, write_addr | (flags << 16));
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} else if (is_draw_state_control_reg(n)) {
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emu_set_draw_state_reg(emu, n, val);
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}
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}
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static uint32_t
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emu_get_pipe_reg(struct emu *emu, unsigned n)
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{
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assert(n < ARRAY_SIZE(emu->pipe_regs.val));
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return emu->pipe_regs.val[n];
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}
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static void
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emu_set_pipe_reg(struct emu *emu, unsigned n, uint32_t val)
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{
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EMU_PIPE_REG(NRT_DATA);
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EMU_PIPE_REG(NRT_ADDR);
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assert(n < ARRAY_SIZE(emu->pipe_regs.val));
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BITSET_SET(emu->pipe_regs.written, n);
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emu->pipe_regs.val[n] = val;
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/* Some pipe regs have special action on write: */
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if (n == emu_reg_offset(&NRT_DATA)) {
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uintptr_t addr = emu_get_reg64(emu, &NRT_ADDR);
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emu_mem_write_dword(emu, addr, val);
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emu_set_reg64(emu, &NRT_ADDR, addr + 4);
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}
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}
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static uint32_t
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emu_get_gpu_reg(struct emu *emu, unsigned n)
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{
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if (n >= ARRAY_SIZE(emu->gpu_regs.val))
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return 0;
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assert(n < ARRAY_SIZE(emu->gpu_regs.val));
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return emu->gpu_regs.val[n];
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}
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void
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emu_set_gpu_reg(struct emu *emu, unsigned n, uint32_t val)
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{
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if (n >= ARRAY_SIZE(emu->gpu_regs.val))
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return;
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assert(n < ARRAY_SIZE(emu->gpu_regs.val));
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BITSET_SET(emu->gpu_regs.written, n);
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emu->gpu_regs.val[n] = val;
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}
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static bool
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is_pipe_reg_addr(unsigned regoff)
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{
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return regoff > 0xffff;
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}
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static unsigned
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get_reg_addr(struct emu *emu)
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{
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switch (emu->data_mode) {
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case DATA_PIPE:
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case DATA_ADDR: return REG_ADDR;
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case DATA_USRADDR: return REG_USRADDR;
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default:
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unreachable("bad data_mode");
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return 0;
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}
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}
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/* Handle reads for special streaming regs: */
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static uint32_t
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emu_get_fifo_reg(struct emu *emu, unsigned n)
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{
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/* TODO the fifo regs are slurping out of a FIFO that the hw is filling
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* in parallel.. we can use `struct emu_queue` to emulate what is actually
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* happening more accurately
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*/
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if (n == REG_MEMDATA) {
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/* $memdata */
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EMU_CONTROL_REG(MEM_READ_DWORDS);
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EMU_CONTROL_REG(MEM_READ_ADDR);
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unsigned read_dwords = emu_get_reg32(emu, &MEM_READ_DWORDS);
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uintptr_t read_addr = emu_get_reg64(emu, &MEM_READ_ADDR);
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if (read_dwords > 0) {
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emu_set_reg32(emu, &MEM_READ_DWORDS, read_dwords - 1);
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emu_set_reg64(emu, &MEM_READ_ADDR, read_addr + 4);
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}
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return emu_mem_read_dword(emu, read_addr);
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} else if (n == REG_REGDATA) {
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/* $regdata */
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EMU_CONTROL_REG(REG_READ_DWORDS);
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EMU_CONTROL_REG(REG_READ_ADDR);
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unsigned read_dwords = emu_get_reg32(emu, ®_READ_DWORDS);
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unsigned read_addr = emu_get_reg32(emu, ®_READ_ADDR);
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/* I think if the fw doesn't write REG_READ_DWORDS before
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* REG_READ_ADDR, it just ends up with a single value written
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* into the FIFO that $regdata is consuming from:
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*/
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if (read_dwords > 0) {
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emu_set_reg32(emu, ®_READ_DWORDS, read_dwords - 1);
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emu_set_reg32(emu, ®_READ_ADDR, read_addr + 1);
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}
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return emu_get_gpu_reg(emu, read_addr);
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} else if (n == REG_DATA) {
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/* $data */
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do {
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uint32_t rem = emu->gpr_regs.val[REG_REM];
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assert(rem >= 0);
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uint32_t val;
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if (emu_queue_pop(&emu->roq, &val)) {
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emu_set_gpr_reg(emu, REG_REM, --rem);
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return val;
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}
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/* If FIFO is empty, prompt for more input: */
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printf("FIFO empty, input a packet!\n");
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emu->run_mode = false;
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emu_main_prompt(emu);
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} while (true);
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} else {
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unreachable("not a FIFO reg");
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return 0;
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}
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}
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static void
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emu_set_fifo_reg(struct emu *emu, unsigned n, uint32_t val)
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{
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if ((n == REG_ADDR) || (n == REG_USRADDR)) {
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emu->data_mode = (n == REG_ADDR) ? DATA_ADDR : DATA_USRADDR;
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/* Treat these as normal register writes so we can see
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* updated values in the output as we step thru the
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* instructions:
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*/
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emu->gpr_regs.val[n] = val;
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BITSET_SET(emu->gpr_regs.written, n);
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if (is_pipe_reg_addr(val)) {
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/* "void" pipe regs don't have a value to write, so just
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* treat it as writing zero to the pipe reg:
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*/
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if (afuc_pipe_reg_is_void(val >> 24))
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emu_set_pipe_reg(emu, val >> 24, 0);
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emu->data_mode = DATA_PIPE;
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}
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} else if (n == REG_DATA) {
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unsigned reg = get_reg_addr(emu);
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unsigned regoff = emu->gpr_regs.val[reg];
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if (is_pipe_reg_addr(regoff)) {
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/* writes pipe registers: */
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assert(!(regoff & 0xfbffff));
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/* If b18 is set, don't auto-increment dest addr.. and if we
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* do auto-increment, we only increment the high 8b
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*
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* Note that we bypass emu_set_gpr_reg() in this case because
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* auto-incrementing isn't triggering a write to "void" pipe
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* regs.
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*/
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if (!(regoff & 0x40000)) {
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emu->gpr_regs.val[reg] = regoff + 0x01000000;
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BITSET_SET(emu->gpr_regs.written, reg);
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}
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emu_set_pipe_reg(emu, regoff >> 24, val);
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} else {
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/* writes to gpu registers: */
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emu_set_gpr_reg(emu, reg, regoff+1);
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emu_set_gpu_reg(emu, regoff, val);
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}
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}
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}
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uint32_t
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emu_get_gpr_reg(struct emu *emu, unsigned n)
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{
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assert(n < ARRAY_SIZE(emu->gpr_regs.val));
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/* Handle special regs: */
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switch (n) {
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case 0x00:
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return 0;
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case REG_MEMDATA:
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case REG_REGDATA:
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case REG_DATA:
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return emu_get_fifo_reg(emu, n);
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default:
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return emu->gpr_regs.val[n];
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}
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}
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void
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emu_set_gpr_reg(struct emu *emu, unsigned n, uint32_t val)
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{
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assert(n < ARRAY_SIZE(emu->gpr_regs.val));
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switch (n) {
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case REG_ADDR:
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case REG_USRADDR:
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case REG_DATA:
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emu_set_fifo_reg(emu, n, val);
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break;
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default:
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emu->gpr_regs.val[n] = val;
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BITSET_SET(emu->gpr_regs.written, n);
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break;
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}
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}
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/*
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* Control/pipe register accessor helpers:
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*/
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struct emu_reg_accessor {
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unsigned (*get_offset)(const char *name);
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uint32_t (*get)(struct emu *emu, unsigned n);
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void (*set)(struct emu *emu, unsigned n, uint32_t val);
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};
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const struct emu_reg_accessor emu_control_accessor = {
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.get_offset = afuc_control_reg,
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.get = emu_get_control_reg,
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.set = emu_set_control_reg,
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};
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const struct emu_reg_accessor emu_pipe_accessor = {
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.get_offset = afuc_pipe_reg,
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.get = emu_get_pipe_reg,
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.set = emu_set_pipe_reg,
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};
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const struct emu_reg_accessor emu_gpu_accessor = {
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.get_offset = afuc_gpu_reg,
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.get = emu_get_gpu_reg,
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.set = emu_set_gpu_reg,
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};
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unsigned
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emu_reg_offset(struct emu_reg *reg)
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{
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if (reg->offset == ~0)
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reg->offset = reg->accessor->get_offset(reg->name);
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return reg->offset;
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}
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uint32_t
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emu_get_reg32(struct emu *emu, struct emu_reg *reg)
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{
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return reg->accessor->get(emu, emu_reg_offset(reg));
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}
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uint64_t
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emu_get_reg64(struct emu *emu, struct emu_reg *reg)
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{
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uint64_t val = reg->accessor->get(emu, emu_reg_offset(reg) + 1);
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val <<= 32;
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val |= reg->accessor->get(emu, emu_reg_offset(reg));
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return val;
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}
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void
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emu_set_reg32(struct emu *emu, struct emu_reg *reg, uint32_t val)
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{
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reg->accessor->set(emu, emu_reg_offset(reg), val);
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}
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void
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emu_set_reg64(struct emu *emu, struct emu_reg *reg, uint64_t val)
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{
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reg->accessor->set(emu, emu_reg_offset(reg), val);
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reg->accessor->set(emu, emu_reg_offset(reg) + 1, val >> 32);
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}
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