486 lines
16 KiB
C
486 lines
16 KiB
C
/*
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* Copyright © 2016 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/**
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* @file qpu_instr.h
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*
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* Definitions of the unpacked form of QPU instructions. Assembly and
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* disassembly will use this for talking about instructions, with qpu_encode.c
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* and qpu_decode.c handling the pack and unpack of the actual 64-bit QPU
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* instruction.
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*/
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#ifndef QPU_INSTR_H
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#define QPU_INSTR_H
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#include <stdbool.h>
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#include <stdint.h>
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#include "util/macros.h"
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struct v3d_device_info;
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struct v3d_qpu_sig {
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bool thrsw:1;
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bool ldunif:1;
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bool ldunifa:1;
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bool ldunifrf:1;
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bool ldunifarf:1;
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bool ldtmu:1;
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bool ldvary:1;
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bool ldvpm:1;
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bool ldtlb:1;
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bool ldtlbu:1;
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bool small_imm:1;
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bool ucb:1;
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bool rotate:1;
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bool wrtmuc:1;
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};
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enum v3d_qpu_cond {
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V3D_QPU_COND_NONE,
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V3D_QPU_COND_IFA,
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V3D_QPU_COND_IFB,
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V3D_QPU_COND_IFNA,
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V3D_QPU_COND_IFNB,
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};
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enum v3d_qpu_pf {
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V3D_QPU_PF_NONE,
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V3D_QPU_PF_PUSHZ,
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V3D_QPU_PF_PUSHN,
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V3D_QPU_PF_PUSHC,
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};
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enum v3d_qpu_uf {
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V3D_QPU_UF_NONE,
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V3D_QPU_UF_ANDZ,
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V3D_QPU_UF_ANDNZ,
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V3D_QPU_UF_NORNZ,
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V3D_QPU_UF_NORZ,
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V3D_QPU_UF_ANDN,
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V3D_QPU_UF_ANDNN,
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V3D_QPU_UF_NORNN,
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V3D_QPU_UF_NORN,
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V3D_QPU_UF_ANDC,
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V3D_QPU_UF_ANDNC,
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V3D_QPU_UF_NORNC,
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V3D_QPU_UF_NORC,
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};
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enum v3d_qpu_waddr {
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V3D_QPU_WADDR_R0 = 0,
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V3D_QPU_WADDR_R1 = 1,
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V3D_QPU_WADDR_R2 = 2,
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V3D_QPU_WADDR_R3 = 3,
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V3D_QPU_WADDR_R4 = 4,
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V3D_QPU_WADDR_R5 = 5,
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V3D_QPU_WADDR_NOP = 6,
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V3D_QPU_WADDR_TLB = 7,
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V3D_QPU_WADDR_TLBU = 8,
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V3D_QPU_WADDR_TMU = 9, /* V3D 3.x */
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V3D_QPU_WADDR_UNIFA = 9, /* V3D 4.x */
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V3D_QPU_WADDR_TMUL = 10,
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V3D_QPU_WADDR_TMUD = 11,
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V3D_QPU_WADDR_TMUA = 12,
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V3D_QPU_WADDR_TMUAU = 13,
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V3D_QPU_WADDR_VPM = 14,
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V3D_QPU_WADDR_VPMU = 15,
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V3D_QPU_WADDR_SYNC = 16,
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V3D_QPU_WADDR_SYNCU = 17,
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V3D_QPU_WADDR_SYNCB = 18,
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V3D_QPU_WADDR_RECIP = 19,
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V3D_QPU_WADDR_RSQRT = 20,
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V3D_QPU_WADDR_EXP = 21,
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V3D_QPU_WADDR_LOG = 22,
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V3D_QPU_WADDR_SIN = 23,
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V3D_QPU_WADDR_RSQRT2 = 24,
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V3D_QPU_WADDR_TMUC = 32,
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V3D_QPU_WADDR_TMUS = 33,
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V3D_QPU_WADDR_TMUT = 34,
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V3D_QPU_WADDR_TMUR = 35,
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V3D_QPU_WADDR_TMUI = 36,
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V3D_QPU_WADDR_TMUB = 37,
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V3D_QPU_WADDR_TMUDREF = 38,
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V3D_QPU_WADDR_TMUOFF = 39,
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V3D_QPU_WADDR_TMUSCM = 40,
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V3D_QPU_WADDR_TMUSF = 41,
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V3D_QPU_WADDR_TMUSLOD = 42,
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V3D_QPU_WADDR_TMUHS = 43,
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V3D_QPU_WADDR_TMUHSCM = 44,
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V3D_QPU_WADDR_TMUHSF = 45,
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V3D_QPU_WADDR_TMUHSLOD = 46,
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V3D_QPU_WADDR_R5REP = 55,
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};
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struct v3d_qpu_flags {
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enum v3d_qpu_cond ac, mc;
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enum v3d_qpu_pf apf, mpf;
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enum v3d_qpu_uf auf, muf;
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};
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enum v3d_qpu_add_op {
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V3D_QPU_A_FADD,
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V3D_QPU_A_FADDNF,
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V3D_QPU_A_VFPACK,
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V3D_QPU_A_ADD,
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V3D_QPU_A_SUB,
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V3D_QPU_A_FSUB,
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V3D_QPU_A_MIN,
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V3D_QPU_A_MAX,
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V3D_QPU_A_UMIN,
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V3D_QPU_A_UMAX,
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V3D_QPU_A_SHL,
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V3D_QPU_A_SHR,
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V3D_QPU_A_ASR,
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V3D_QPU_A_ROR,
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V3D_QPU_A_FMIN,
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V3D_QPU_A_FMAX,
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V3D_QPU_A_VFMIN,
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V3D_QPU_A_AND,
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V3D_QPU_A_OR,
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V3D_QPU_A_XOR,
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V3D_QPU_A_VADD,
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V3D_QPU_A_VSUB,
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V3D_QPU_A_NOT,
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V3D_QPU_A_NEG,
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V3D_QPU_A_FLAPUSH,
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V3D_QPU_A_FLBPUSH,
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V3D_QPU_A_FLPOP,
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V3D_QPU_A_RECIP,
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V3D_QPU_A_SETMSF,
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V3D_QPU_A_SETREVF,
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V3D_QPU_A_NOP,
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V3D_QPU_A_TIDX,
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V3D_QPU_A_EIDX,
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V3D_QPU_A_LR,
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V3D_QPU_A_VFLA,
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V3D_QPU_A_VFLNA,
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V3D_QPU_A_VFLB,
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V3D_QPU_A_VFLNB,
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V3D_QPU_A_FXCD,
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V3D_QPU_A_XCD,
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V3D_QPU_A_FYCD,
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V3D_QPU_A_YCD,
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V3D_QPU_A_MSF,
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V3D_QPU_A_REVF,
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V3D_QPU_A_VDWWT,
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V3D_QPU_A_IID,
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V3D_QPU_A_SAMPID,
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V3D_QPU_A_BARRIERID,
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V3D_QPU_A_TMUWT,
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V3D_QPU_A_VPMSETUP,
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V3D_QPU_A_VPMWT,
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V3D_QPU_A_FLAFIRST,
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V3D_QPU_A_FLNAFIRST,
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V3D_QPU_A_LDVPMV_IN,
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V3D_QPU_A_LDVPMV_OUT,
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V3D_QPU_A_LDVPMD_IN,
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V3D_QPU_A_LDVPMD_OUT,
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V3D_QPU_A_LDVPMP,
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V3D_QPU_A_RSQRT,
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V3D_QPU_A_EXP,
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V3D_QPU_A_LOG,
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V3D_QPU_A_SIN,
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V3D_QPU_A_RSQRT2,
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V3D_QPU_A_LDVPMG_IN,
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V3D_QPU_A_LDVPMG_OUT,
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V3D_QPU_A_FCMP,
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V3D_QPU_A_VFMAX,
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V3D_QPU_A_FROUND,
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V3D_QPU_A_FTOIN,
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V3D_QPU_A_FTRUNC,
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V3D_QPU_A_FTOIZ,
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V3D_QPU_A_FFLOOR,
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V3D_QPU_A_FTOUZ,
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V3D_QPU_A_FCEIL,
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V3D_QPU_A_FTOC,
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V3D_QPU_A_FDX,
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V3D_QPU_A_FDY,
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V3D_QPU_A_STVPMV,
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V3D_QPU_A_STVPMD,
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V3D_QPU_A_STVPMP,
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V3D_QPU_A_ITOF,
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V3D_QPU_A_CLZ,
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V3D_QPU_A_UTOF,
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};
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enum v3d_qpu_mul_op {
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V3D_QPU_M_ADD,
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V3D_QPU_M_SUB,
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V3D_QPU_M_UMUL24,
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V3D_QPU_M_VFMUL,
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V3D_QPU_M_SMUL24,
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V3D_QPU_M_MULTOP,
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V3D_QPU_M_FMOV,
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V3D_QPU_M_MOV,
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V3D_QPU_M_NOP,
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V3D_QPU_M_FMUL,
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};
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enum v3d_qpu_output_pack {
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V3D_QPU_PACK_NONE,
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/**
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* Convert to 16-bit float, put in low 16 bits of destination leaving
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* high unmodified.
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*/
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V3D_QPU_PACK_L,
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/**
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* Convert to 16-bit float, put in high 16 bits of destination leaving
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* low unmodified.
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*/
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V3D_QPU_PACK_H,
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};
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enum v3d_qpu_input_unpack {
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/**
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* No-op input unpacking. Note that this enum's value doesn't match
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* the packed QPU instruction value of the field (we use 0 so that the
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* default on new instruction creation is no-op).
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*/
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V3D_QPU_UNPACK_NONE,
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/** Absolute value. Only available for some operations. */
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V3D_QPU_UNPACK_ABS,
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/** Convert low 16 bits from 16-bit float to 32-bit float. */
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V3D_QPU_UNPACK_L,
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/** Convert high 16 bits from 16-bit float to 32-bit float. */
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V3D_QPU_UNPACK_H,
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/** Convert to 16f and replicate it to the high bits. */
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V3D_QPU_UNPACK_REPLICATE_32F_16,
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/** Replicate low 16 bits to high */
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V3D_QPU_UNPACK_REPLICATE_L_16,
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/** Replicate high 16 bits to low */
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V3D_QPU_UNPACK_REPLICATE_H_16,
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/** Swap high and low 16 bits */
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V3D_QPU_UNPACK_SWAP_16,
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};
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enum v3d_qpu_mux {
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V3D_QPU_MUX_R0,
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V3D_QPU_MUX_R1,
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V3D_QPU_MUX_R2,
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V3D_QPU_MUX_R3,
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V3D_QPU_MUX_R4,
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V3D_QPU_MUX_R5,
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V3D_QPU_MUX_A,
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V3D_QPU_MUX_B,
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};
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struct v3d_qpu_alu_instr {
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struct {
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enum v3d_qpu_add_op op;
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enum v3d_qpu_mux a, b;
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uint8_t waddr;
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bool magic_write;
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enum v3d_qpu_output_pack output_pack;
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enum v3d_qpu_input_unpack a_unpack;
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enum v3d_qpu_input_unpack b_unpack;
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} add;
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struct {
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enum v3d_qpu_mul_op op;
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enum v3d_qpu_mux a, b;
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uint8_t waddr;
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bool magic_write;
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enum v3d_qpu_output_pack output_pack;
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enum v3d_qpu_input_unpack a_unpack;
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enum v3d_qpu_input_unpack b_unpack;
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} mul;
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};
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enum v3d_qpu_branch_cond {
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V3D_QPU_BRANCH_COND_ALWAYS,
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V3D_QPU_BRANCH_COND_A0,
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V3D_QPU_BRANCH_COND_NA0,
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V3D_QPU_BRANCH_COND_ALLA,
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V3D_QPU_BRANCH_COND_ANYNA,
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V3D_QPU_BRANCH_COND_ANYA,
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V3D_QPU_BRANCH_COND_ALLNA,
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};
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enum v3d_qpu_msfign {
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/** Ignore multisample flags when determining branch condition. */
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V3D_QPU_MSFIGN_NONE,
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/**
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* If no multisample flags are set in the lane (a pixel in the FS, a
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* vertex in the VS), ignore the lane's condition when computing the
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* branch condition.
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*/
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V3D_QPU_MSFIGN_P,
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/**
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* If no multisample flags are set in a 2x2 quad in the FS, ignore the
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* quad's a/b conditions.
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*/
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V3D_QPU_MSFIGN_Q,
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};
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enum v3d_qpu_branch_dest {
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V3D_QPU_BRANCH_DEST_ABS,
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V3D_QPU_BRANCH_DEST_REL,
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V3D_QPU_BRANCH_DEST_LINK_REG,
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V3D_QPU_BRANCH_DEST_REGFILE,
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};
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struct v3d_qpu_branch_instr {
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enum v3d_qpu_branch_cond cond;
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enum v3d_qpu_msfign msfign;
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/** Selects how to compute the new IP if the branch is taken. */
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enum v3d_qpu_branch_dest bdi;
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/**
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* Selects how to compute the new uniforms pointer if the branch is
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* taken. (ABS/REL implicitly load a uniform and use that)
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*/
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enum v3d_qpu_branch_dest bdu;
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/**
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* If set, then udest determines how the uniform stream will branch,
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* otherwise the uniform stream is left as is.
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*/
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bool ub;
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uint8_t raddr_a;
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uint32_t offset;
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};
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enum v3d_qpu_instr_type {
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V3D_QPU_INSTR_TYPE_ALU,
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V3D_QPU_INSTR_TYPE_BRANCH,
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};
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struct v3d_qpu_instr {
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enum v3d_qpu_instr_type type;
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struct v3d_qpu_sig sig;
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uint8_t sig_addr;
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bool sig_magic; /* If the signal writes to a magic address */
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uint8_t raddr_a;
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uint8_t raddr_b;
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struct v3d_qpu_flags flags;
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union {
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struct v3d_qpu_alu_instr alu;
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struct v3d_qpu_branch_instr branch;
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};
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};
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const char *v3d_qpu_magic_waddr_name(const struct v3d_device_info *devinfo,
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enum v3d_qpu_waddr waddr);
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const char *v3d_qpu_add_op_name(enum v3d_qpu_add_op op);
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const char *v3d_qpu_mul_op_name(enum v3d_qpu_mul_op op);
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const char *v3d_qpu_cond_name(enum v3d_qpu_cond cond);
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const char *v3d_qpu_pf_name(enum v3d_qpu_pf pf);
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const char *v3d_qpu_uf_name(enum v3d_qpu_uf uf);
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const char *v3d_qpu_pack_name(enum v3d_qpu_output_pack pack);
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const char *v3d_qpu_unpack_name(enum v3d_qpu_input_unpack unpack);
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const char *v3d_qpu_branch_cond_name(enum v3d_qpu_branch_cond cond);
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const char *v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign);
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enum v3d_qpu_cond v3d_qpu_cond_invert(enum v3d_qpu_cond cond) ATTRIBUTE_CONST;
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bool v3d_qpu_add_op_has_dst(enum v3d_qpu_add_op op);
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bool v3d_qpu_mul_op_has_dst(enum v3d_qpu_mul_op op);
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int v3d_qpu_add_op_num_src(enum v3d_qpu_add_op op);
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int v3d_qpu_mul_op_num_src(enum v3d_qpu_mul_op op);
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bool v3d_qpu_sig_pack(const struct v3d_device_info *devinfo,
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const struct v3d_qpu_sig *sig,
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uint32_t *packed_sig);
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bool v3d_qpu_sig_unpack(const struct v3d_device_info *devinfo,
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uint32_t packed_sig,
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struct v3d_qpu_sig *sig);
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bool
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v3d_qpu_flags_pack(const struct v3d_device_info *devinfo,
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const struct v3d_qpu_flags *cond,
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uint32_t *packed_cond);
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bool
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v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo,
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uint32_t packed_cond,
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struct v3d_qpu_flags *cond);
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bool
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v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo,
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uint32_t value,
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uint32_t *packed_small_immediate);
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bool
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v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo,
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uint32_t packed_small_immediate,
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uint32_t *small_immediate);
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bool
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v3d_qpu_instr_pack(const struct v3d_device_info *devinfo,
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const struct v3d_qpu_instr *instr,
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uint64_t *packed_instr);
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bool
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v3d_qpu_instr_unpack(const struct v3d_device_info *devinfo,
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uint64_t packed_instr,
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struct v3d_qpu_instr *instr);
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bool v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
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bool v3d_qpu_magic_waddr_is_tmu(const struct v3d_device_info *devinfo,
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enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
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bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
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bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
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bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
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bool v3d_qpu_magic_waddr_loads_unif(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
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bool v3d_qpu_uses_tlb(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_instr_is_sfu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_uses_sfu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_writes_tmu(const struct v3d_device_info *devinfo,
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const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_writes_tmu_not_tmuc(const struct v3d_device_info *devinfo,
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const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_writes_r3(const struct v3d_device_info *devinfo,
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const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
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bool v3d_qpu_writes_r4(const struct v3d_device_info *devinfo,
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const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
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bool v3d_qpu_writes_r5(const struct v3d_device_info *devinfo,
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const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
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bool v3d_qpu_writes_accum(const struct v3d_device_info *devinfo,
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const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_waits_on_tmu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux);
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bool v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_waits_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_reads_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_writes_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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|
bool v3d_qpu_reads_or_writes_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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bool v3d_qpu_reads_flags(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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|
bool v3d_qpu_writes_flags(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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|
bool v3d_qpu_writes_unifa(const struct v3d_device_info *devinfo,
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|
const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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|
bool v3d_qpu_sig_writes_address(const struct v3d_device_info *devinfo,
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|
const struct v3d_qpu_sig *sig) ATTRIBUTE_CONST;
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|
bool v3d_qpu_unpacks_f32(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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|
bool v3d_qpu_unpacks_f16(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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|
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bool v3d_qpu_is_nop(struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
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#endif
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