344 lines
13 KiB
C
344 lines
13 KiB
C
/*
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* Copyright © 2012 Intel Corporation
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* Copyright © 2016 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#define MAX_INSTRUCTION (1 << 30)
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#include "util/ralloc.h"
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#include "util/register_allocate.h"
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#include "v3d_compiler.h"
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/* Keeps track of conditional / partial writes in a block */
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struct partial_update_state {
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/* Instruction doing a conditional or partial write */
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struct qinst *inst;
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/* Instruction that set the flags for the conditional write */
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struct qinst *flags_inst;
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};
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static int
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vir_reg_to_var(struct qreg reg)
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{
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if (reg.file == QFILE_TEMP)
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return reg.index;
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return -1;
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}
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static void
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vir_setup_use(struct v3d_compile *c, struct qblock *block, int ip,
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struct partial_update_state *partial_update_ht, struct qinst *inst,
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struct qreg src, struct qinst *flags_inst)
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{
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int var = vir_reg_to_var(src);
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if (var == -1)
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return;
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c->temp_start[var] = MIN2(c->temp_start[var], ip);
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c->temp_end[var] = MAX2(c->temp_end[var], ip);
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/* The use[] bitset marks when the block makes
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* use of a variable without having completely
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* defined that variable within the block.
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*/
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if (!BITSET_TEST(block->def, var)) {
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/* If this use of var is conditional and the condition
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* and flags match those of a previous instruction
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* in the same block partially defining var then we
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* consider var completely defined within the block.
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*/
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if (BITSET_TEST(block->defout, var)) {
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struct partial_update_state *state =
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&partial_update_ht[var];
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if (state->inst) {
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if (vir_get_cond(inst) == vir_get_cond(state->inst) &&
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flags_inst == state->flags_inst) {
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return;
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}
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}
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}
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BITSET_SET(block->use, var);
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}
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}
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/* The def[] bitset marks when an initialization in a
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* block completely screens off previous updates of
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* that variable.
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*/
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static void
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vir_setup_def(struct v3d_compile *c, struct qblock *block, int ip,
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struct partial_update_state *partial_update, struct qinst *inst,
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struct qinst *flags_inst)
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{
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if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU)
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return;
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int var = vir_reg_to_var(inst->dst);
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if (var == -1)
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return;
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c->temp_start[var] = MIN2(c->temp_start[var], ip);
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c->temp_end[var] = MAX2(c->temp_end[var], ip);
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/* Mark the block as having a (partial) def of the var. */
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BITSET_SET(block->defout, var);
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/* If we've already tracked this as a def that screens off previous
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* uses, or already used it within the block, there's nothing to do.
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*/
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if (BITSET_TEST(block->use, var) || BITSET_TEST(block->def, var))
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return;
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/* Easy, common case: unconditional full register update.*/
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if ((inst->qpu.flags.ac == V3D_QPU_COND_NONE &&
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inst->qpu.flags.mc == V3D_QPU_COND_NONE) &&
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inst->qpu.alu.add.output_pack == V3D_QPU_PACK_NONE &&
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inst->qpu.alu.mul.output_pack == V3D_QPU_PACK_NONE) {
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BITSET_SET(block->def, var);
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return;
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}
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/* Keep track of conditional writes.
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*
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* Notice that the dst's live range for a conditional or partial writes
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* will get extended up the control flow to the top of the program until
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* we find a full write, making register allocation more difficult, so
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* we should try our best to keep track of these and figure out if a
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* combination of them actually writes the entire register so we can
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* stop that process early and reduce liveness.
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*
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* FIXME: Track partial updates via pack/unpack.
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*/
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struct partial_update_state *state = &partial_update[var];
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if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
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inst->qpu.flags.mc != V3D_QPU_COND_NONE) {
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state->inst = inst;
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state->flags_inst = flags_inst;
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}
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}
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/* Sets up the def/use arrays for when variables are used-before-defined or
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* defined-before-used in the block.
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*
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* Also initializes the temp_start/temp_end to cover just the instruction IPs
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* where the variable is used, which will be extended later in
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* vir_compute_start_end().
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*/
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static void
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vir_setup_def_use(struct v3d_compile *c)
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{
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struct partial_update_state *partial_update =
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rzalloc_array(c, struct partial_update_state, c->num_temps);
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int ip = 0;
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vir_for_each_block(block, c) {
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block->start_ip = ip;
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memset(partial_update, 0,
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sizeof(struct partial_update_state) * c->num_temps);
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struct qinst *flags_inst = NULL;
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vir_for_each_inst(inst, block) {
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for (int i = 0; i < vir_get_nsrc(inst); i++) {
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vir_setup_use(c, block, ip, partial_update,
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inst, inst->src[i], flags_inst);
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}
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vir_setup_def(c, block, ip, partial_update,
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inst, flags_inst);
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if (inst->qpu.flags.apf != V3D_QPU_PF_NONE ||
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inst->qpu.flags.mpf != V3D_QPU_PF_NONE) {
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flags_inst = inst;
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}
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if (inst->qpu.flags.auf != V3D_QPU_UF_NONE ||
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inst->qpu.flags.muf != V3D_QPU_UF_NONE) {
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flags_inst = NULL;
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}
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/* Payload registers: r0/1/2 contain W, centroid W,
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* and Z at program start. Register allocation will
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* force their nodes to R0/1/2.
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*/
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if (inst->src[0].file == QFILE_REG) {
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switch (inst->src[0].index) {
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case 0:
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case 1:
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case 2:
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c->temp_start[inst->dst.index] = 0;
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break;
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}
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}
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ip++;
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}
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block->end_ip = ip;
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}
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ralloc_free(partial_update);
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}
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static bool
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vir_live_variables_dataflow(struct v3d_compile *c, int bitset_words)
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{
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bool cont = false;
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vir_for_each_block_rev(block, c) {
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/* Update live_out: Any successor using the variable
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* on entrance needs us to have the variable live on
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* exit.
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*/
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vir_for_each_successor(succ, block) {
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_live_out = (succ->live_in[i] &
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~block->live_out[i]);
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if (new_live_out) {
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block->live_out[i] |= new_live_out;
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cont = true;
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}
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}
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}
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/* Update live_in */
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_live_in = (block->use[i] |
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(block->live_out[i] &
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~block->def[i]));
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if (new_live_in & ~block->live_in[i]) {
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block->live_in[i] |= new_live_in;
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cont = true;
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}
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}
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}
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return cont;
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}
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static bool
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vir_live_variables_defin_defout_dataflow(struct v3d_compile *c, int bitset_words)
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{
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bool cont = false;
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vir_for_each_block_rev(block, c) {
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/* Propagate defin/defout down the successors to produce the
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* union of blocks with a reachable (partial) definition of
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* the var.
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*
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* This keeps a conditional first write to a reg from
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* extending its lifetime back to the start of the program.
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*/
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vir_for_each_successor(succ, block) {
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_def = (block->defout[i] &
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~succ->defin[i]);
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succ->defin[i] |= new_def;
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succ->defout[i] |= new_def;
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cont |= new_def;
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}
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}
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}
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return cont;
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}
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/**
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* Extend the start/end ranges for each variable to account for the
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* new information calculated from control flow.
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*/
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static void
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vir_compute_start_end(struct v3d_compile *c, int num_vars)
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{
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vir_for_each_block(block, c) {
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for (int i = 0; i < num_vars; i++) {
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if (BITSET_TEST(block->live_in, i) &&
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BITSET_TEST(block->defin, i)) {
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c->temp_start[i] = MIN2(c->temp_start[i],
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block->start_ip);
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c->temp_end[i] = MAX2(c->temp_end[i],
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block->start_ip);
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}
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if (BITSET_TEST(block->live_out, i) &&
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BITSET_TEST(block->defout, i)) {
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c->temp_start[i] = MIN2(c->temp_start[i],
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block->end_ip);
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c->temp_end[i] = MAX2(c->temp_end[i],
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block->end_ip);
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}
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}
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}
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}
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void
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vir_calculate_live_intervals(struct v3d_compile *c)
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{
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int bitset_words = BITSET_WORDS(c->num_temps);
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/* We may be called more than once if we've rearranged the program to
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* try to get register allocation to succeed.
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*/
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if (c->temp_start) {
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ralloc_free(c->temp_start);
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ralloc_free(c->temp_end);
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vir_for_each_block(block, c) {
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ralloc_free(block->def);
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ralloc_free(block->use);
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ralloc_free(block->live_in);
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ralloc_free(block->live_out);
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}
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}
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c->temp_start = rzalloc_array(c, int, c->num_temps);
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c->temp_end = rzalloc_array(c, int, c->num_temps);
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for (int i = 0; i < c->num_temps; i++) {
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c->temp_start[i] = MAX_INSTRUCTION;
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c->temp_end[i] = -1;
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}
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vir_for_each_block(block, c) {
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block->def = rzalloc_array(c, BITSET_WORD, bitset_words);
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block->defin = rzalloc_array(c, BITSET_WORD, bitset_words);
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block->defout = rzalloc_array(c, BITSET_WORD, bitset_words);
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block->use = rzalloc_array(c, BITSET_WORD, bitset_words);
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block->live_in = rzalloc_array(c, BITSET_WORD, bitset_words);
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block->live_out = rzalloc_array(c, BITSET_WORD, bitset_words);
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}
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vir_setup_def_use(c);
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while (vir_live_variables_dataflow(c, bitset_words))
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;
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while (vir_live_variables_defin_defout_dataflow(c, bitset_words))
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;
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vir_compute_start_end(c, c->num_temps);
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c->live_intervals_valid = true;
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}
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