196 lines
7.9 KiB
C
196 lines
7.9 KiB
C
/*
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* Copyright © 2016-2018 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "v3d_compiler.h"
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/* We don't do any address packing. */
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#define __gen_user_data void
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#define __gen_address_type uint32_t
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#define __gen_address_offset(reloc) (*reloc)
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#define __gen_emit_reloc(cl, reloc)
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#include "cle/v3d_packet_v33_pack.h"
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void
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v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
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{
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/* FIXME: We don't bother implementing pipelining for texture reads
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* for any pre 4.x hardware. It should be straight forward to do but
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* we are not really testing or even targetting this hardware at
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* present.
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*/
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ntq_flush_tmu(c);
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unsigned unit = instr->texture_index;
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struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
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V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_header,
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.fetch_sample_mode = instr->op == nir_texop_txf,
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};
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struct V3D33_TEXTURE_UNIFORM_PARAMETER_1_CFG_MODE1 p1_unpacked = {
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};
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switch (instr->sampler_dim) {
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case GLSL_SAMPLER_DIM_1D:
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if (instr->is_array)
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p0_unpacked.lookup_type = TEXTURE_1D_ARRAY;
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else
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p0_unpacked.lookup_type = TEXTURE_1D;
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break;
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case GLSL_SAMPLER_DIM_2D:
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case GLSL_SAMPLER_DIM_RECT:
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if (instr->is_array)
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p0_unpacked.lookup_type = TEXTURE_2D_ARRAY;
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else
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p0_unpacked.lookup_type = TEXTURE_2D;
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break;
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case GLSL_SAMPLER_DIM_3D:
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p0_unpacked.lookup_type = TEXTURE_3D;
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break;
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case GLSL_SAMPLER_DIM_CUBE:
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p0_unpacked.lookup_type = TEXTURE_CUBE_MAP;
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break;
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default:
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unreachable("Bad sampler type");
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}
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struct qreg coords[5];
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int next_coord = 0;
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for (unsigned i = 0; i < instr->num_srcs; i++) {
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switch (instr->src[i].src_type) {
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case nir_tex_src_coord:
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for (int j = 0; j < instr->coord_components; j++) {
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coords[next_coord++] =
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ntq_get_src(c, instr->src[i].src, j);
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}
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if (instr->coord_components < 2)
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coords[next_coord++] = vir_uniform_f(c, 0.5);
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break;
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case nir_tex_src_bias:
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coords[next_coord++] =
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ntq_get_src(c, instr->src[i].src, 0);
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p0_unpacked.bias_supplied = true;
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break;
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case nir_tex_src_lod:
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coords[next_coord++] =
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vir_FADD(c,
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ntq_get_src(c, instr->src[i].src, 0),
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vir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL,
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unit));
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if (instr->op != nir_texop_txf &&
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instr->op != nir_texop_tg4) {
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p0_unpacked.disable_autolod_use_bias_only = true;
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}
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break;
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case nir_tex_src_comparator:
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coords[next_coord++] =
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ntq_get_src(c, instr->src[i].src, 0);
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p0_unpacked.shadow = true;
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break;
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case nir_tex_src_offset: {
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p0_unpacked.texel_offset_for_s_coordinate =
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nir_src_comp_as_int(instr->src[i].src, 0);
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if (instr->coord_components >= 2)
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p0_unpacked.texel_offset_for_t_coordinate =
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nir_src_comp_as_int(instr->src[i].src, 1);
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if (instr->coord_components >= 3)
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p0_unpacked.texel_offset_for_r_coordinate =
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nir_src_comp_as_int(instr->src[i].src, 2);
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break;
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}
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default:
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unreachable("unknown texture source");
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}
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}
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/* Limit the number of channels returned to both how many the NIR
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* instruction writes and how many the instruction could produce.
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*/
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p1_unpacked.return_words_of_texture_data =
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instr->dest.is_ssa ?
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nir_ssa_def_components_read(&instr->dest.ssa) :
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(1 << instr->dest.reg.reg->num_components) - 1;
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uint32_t p0_packed;
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V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
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(uint8_t *)&p0_packed,
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&p0_unpacked);
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uint32_t p1_packed;
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V3D33_TEXTURE_UNIFORM_PARAMETER_1_CFG_MODE1_pack(NULL,
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(uint8_t *)&p1_packed,
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&p1_unpacked);
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/* Load unit number into the address field, which will be be used by
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* the driver to decide which texture to put in the actual address
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* field.
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*/
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p1_packed |= unit << 5;
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/* There is no native support for GL texture rectangle coordinates, so
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* we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
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* 1]).
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*/
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if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
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coords[0] = vir_FMUL(c, coords[0],
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vir_uniform(c, QUNIFORM_TEXRECT_SCALE_X,
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unit));
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coords[1] = vir_FMUL(c, coords[1],
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vir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y,
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unit));
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}
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int texture_u[] = {
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vir_get_uniform_index(c, QUNIFORM_TEXTURE_CONFIG_P0_0 + unit, p0_packed),
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vir_get_uniform_index(c, QUNIFORM_TEXTURE_CONFIG_P1, p1_packed),
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};
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for (int i = 0; i < next_coord; i++) {
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struct qreg dst;
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if (i == next_coord - 1)
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dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUL);
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else
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dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMU);
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struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]);
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if (i < 2)
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tmu->uniform = texture_u[i];
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}
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vir_emit_thrsw(c);
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for (int i = 0; i < 4; i++) {
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if (p1_unpacked.return_words_of_texture_data & (1 << i))
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ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
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}
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}
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