231 lines
8.9 KiB
C
231 lines
8.9 KiB
C
/*
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* Copyright © 2021 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <inttypes.h>
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#include "radv_cs.h"
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#include "radv_private.h"
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#include "sid.h"
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#define SPM_RING_BASE_ALIGN 32
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static bool
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radv_spm_init_bo(struct radv_device *device)
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{
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struct radeon_winsys *ws = device->ws;
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uint64_t size = 32 * 1024 * 1024; /* Default to 1MB. */
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uint16_t sample_interval = 4096; /* Default to 4096 clk. */
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VkResult result;
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device->spm_trace.buffer_size = size;
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device->spm_trace.sample_interval = sample_interval;
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struct radeon_winsys_bo *bo = NULL;
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result = ws->buffer_create(
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ws, size, 4096, RADEON_DOMAIN_VRAM,
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_ZERO_VRAM,
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RADV_BO_PRIORITY_SCRATCH, 0, &bo);
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device->spm_trace.bo = bo;
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if (result != VK_SUCCESS)
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return false;
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result = ws->buffer_make_resident(ws, device->spm_trace.bo, true);
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if (result != VK_SUCCESS)
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return false;
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device->spm_trace.ptr = ws->buffer_map(device->spm_trace.bo);
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if (!device->spm_trace.ptr)
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return false;
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return true;
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}
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static void
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radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs)
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{
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struct ac_spm_trace_data *spm_trace = &device->spm_trace;
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for (uint32_t b = 0; b < spm_trace->num_used_sq_block_sel; b++) {
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struct ac_spm_block_select *sq_block_sel = &spm_trace->sq_block_sel[b];
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const struct ac_spm_counter_select *cntr_sel = &sq_block_sel->counters[0];
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uint32_t reg_base = R_036700_SQ_PERFCOUNTER0_SELECT;
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radeon_set_uconfig_reg_seq(cs, reg_base + b * 4, 1);
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radeon_emit(cs, cntr_sel->sel0 | S_036700_SQC_BANK_MASK(0xf)); /* SQC_BANK_MASK only gfx10 */
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}
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for (uint32_t b = 0; b < spm_trace->num_block_sel; b++) {
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struct ac_spm_block_select *block_sel = &spm_trace->block_sel[b];
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struct ac_pc_block_base *regs = block_sel->b->b->b;
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radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, block_sel->grbm_gfx_index);
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for (unsigned c = 0; c < block_sel->num_counters; c++) {
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const struct ac_spm_counter_select *cntr_sel = &block_sel->counters[c];
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if (!cntr_sel->active)
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continue;
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radeon_set_uconfig_reg_seq(cs, regs->select0[c], 1);
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radeon_emit(cs, cntr_sel->sel0);
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radeon_set_uconfig_reg_seq(cs, regs->select1[c], 1);
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radeon_emit(cs, cntr_sel->sel1);
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}
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}
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/* Restore global broadcasting. */
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radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
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S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
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S_030800_INSTANCE_BROADCAST_WRITES(1));
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}
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void
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radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs)
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{
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struct ac_spm_trace_data *spm_trace = &device->spm_trace;
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uint64_t va = radv_buffer_get_va(spm_trace->bo);
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uint64_t ring_size = spm_trace->buffer_size;
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/* It's required that the ring VA and the size are correctly aligned. */
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assert(!(va & (SPM_RING_BASE_ALIGN - 1)));
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assert(!(ring_size & (SPM_RING_BASE_ALIGN - 1)));
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assert(spm_trace->sample_interval >= 32);
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/* Configure the SPM ring buffer. */
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radeon_set_uconfig_reg(cs, R_037200_RLC_SPM_PERFMON_CNTL,
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S_037200_PERFMON_RING_MODE(0) | /* no stall and no interrupt on overflow */
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S_037200_PERFMON_SAMPLE_INTERVAL(spm_trace->sample_interval)); /* in sclk */
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radeon_set_uconfig_reg(cs, R_037204_RLC_SPM_PERFMON_RING_BASE_LO, va);
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radeon_set_uconfig_reg(cs, R_037208_RLC_SPM_PERFMON_RING_BASE_HI,
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S_037208_RING_BASE_HI(va >> 32));
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radeon_set_uconfig_reg(cs, R_03720C_RLC_SPM_PERFMON_RING_SIZE, ring_size);
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/* Configure the muxsel. */
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uint32_t total_muxsel_lines = 0;
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for (unsigned s = 0; s < AC_SPM_SEGMENT_TYPE_COUNT; s++) {
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total_muxsel_lines += spm_trace->num_muxsel_lines[s];
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}
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radeon_set_uconfig_reg(cs, R_03726C_RLC_SPM_ACCUM_MODE, 0);
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radeon_set_uconfig_reg(cs, R_037210_RLC_SPM_PERFMON_SEGMENT_SIZE, 0);
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radeon_set_uconfig_reg(cs, R_03727C_RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE,
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S_03727C_SE0_NUM_LINE(spm_trace->num_muxsel_lines[0]) |
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S_03727C_SE1_NUM_LINE(spm_trace->num_muxsel_lines[1]) |
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S_03727C_SE2_NUM_LINE(spm_trace->num_muxsel_lines[2]) |
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S_03727C_SE3_NUM_LINE(spm_trace->num_muxsel_lines[3]));
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radeon_set_uconfig_reg(cs, R_037280_RLC_SPM_PERFMON_GLB_SEGMENT_SIZE,
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S_037280_PERFMON_SEGMENT_SIZE(total_muxsel_lines) |
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S_037280_GLOBAL_NUM_LINE(spm_trace->num_muxsel_lines[4]));
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/* Upload each muxsel ram to the RLC. */
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for (unsigned s = 0; s < AC_SPM_SEGMENT_TYPE_COUNT; s++) {
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unsigned rlc_muxsel_addr, rlc_muxsel_data;
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unsigned grbm_gfx_index = S_030800_SH_BROADCAST_WRITES(1) |
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S_030800_INSTANCE_BROADCAST_WRITES(1);
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if (!spm_trace->num_muxsel_lines[s])
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continue;
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if (s == AC_SPM_SEGMENT_TYPE_GLOBAL) {
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grbm_gfx_index |= S_030800_SE_BROADCAST_WRITES(1);
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rlc_muxsel_addr = R_037224_RLC_SPM_GLOBAL_MUXSEL_ADDR;
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rlc_muxsel_data = R_037228_RLC_SPM_GLOBAL_MUXSEL_DATA;
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} else {
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grbm_gfx_index |= S_030800_SE_INDEX(s);
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rlc_muxsel_addr = R_03721C_RLC_SPM_SE_MUXSEL_ADDR;
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rlc_muxsel_data = R_037220_RLC_SPM_SE_MUXSEL_DATA;
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}
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radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, grbm_gfx_index);
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for (unsigned l = 0; l < spm_trace->num_muxsel_lines[s]; l++) {
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uint32_t *data = (uint32_t *)spm_trace->muxsel_lines[s][l].muxsel;
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/* Select MUXSEL_ADDR to point to the next muxsel. */
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radeon_set_uconfig_reg(cs, rlc_muxsel_addr, l * AC_SPM_MUXSEL_LINE_SIZE);
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/* Write the muxsel line configuration with MUXSEL_DATA. */
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + AC_SPM_MUXSEL_LINE_SIZE, 0));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEM_MAPPED_REGISTER) |
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S_370_WR_CONFIRM(1) |
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S_370_ENGINE_SEL(V_370_ME) |
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S_370_WR_ONE_ADDR(1));
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radeon_emit(cs, rlc_muxsel_data >> 2);
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radeon_emit(cs, 0);
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radeon_emit_array(cs, data, AC_SPM_MUXSEL_LINE_SIZE);
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}
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}
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/* Select SPM counters. */
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radv_emit_spm_counters(device, cs);
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}
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bool
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radv_spm_init(struct radv_device *device)
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{
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const struct radeon_info *info = &device->physical_device->rad_info;
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struct ac_perfcounters *pc = &device->physical_device->ac_perfcounters;
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struct ac_spm_counter_create_info spm_counters[] = {
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{TCP, 0, 0x9}, /* Number of L2 requests. */
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{TCP, 0, 0x12}, /* Number of L2 misses. */
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{SQ, 0, 0x14f}, /* Number of SCACHE hits. */
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{SQ, 0, 0x150}, /* Number of SCACHE misses. */
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{SQ, 0, 0x151}, /* Number of SCACHE misses duplicate. */
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{SQ, 0, 0x12c}, /* Number of ICACHE hits. */
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{SQ, 0, 0x12d}, /* Number of ICACHE misses. */
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{SQ, 0, 0x12e}, /* Number of ICACHE misses duplicate. */
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{GL1C, 0, 0xe}, /* Number of GL1C requests. */
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{GL1C, 0, 0x12}, /* Number of GL1C misses. */
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{GL2C, 0, 0x3}, /* Number of GL2C requests. */
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{GL2C, 0, info->gfx_level >= GFX10_3 ? 0x2b : 0x23}, /* Number of GL2C misses. */
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};
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/* We failed to initialize the performance counters. */
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if (!pc->blocks)
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return false;
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if (!ac_init_spm(info, pc, ARRAY_SIZE(spm_counters), spm_counters, &device->spm_trace))
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return false;
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if (!radv_spm_init_bo(device))
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return false;
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return true;
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}
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void
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radv_spm_finish(struct radv_device *device)
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{
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struct radeon_winsys *ws = device->ws;
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if (device->spm_trace.bo) {
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ws->buffer_make_resident(ws, device->spm_trace.bo, false);
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ws->buffer_destroy(ws, device->spm_trace.bo);
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}
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ac_destroy_spm(&device->spm_trace);
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}
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