339 lines
11 KiB
C
339 lines
11 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* Based on radeon_winsys.h which is:
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* Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
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* Copyright 2010 Marek Olšák <maraeo@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef RADV_RADEON_WINSYS_H
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#define RADV_RADEON_WINSYS_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "util/u_math.h"
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#include "util/u_memory.h"
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#include <vulkan/vulkan.h>
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#include "amd_family.h"
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struct radeon_info;
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struct ac_surf_info;
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struct radeon_surf;
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struct vk_sync_type;
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struct vk_sync_wait;
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struct vk_sync_signal;
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enum radeon_bo_domain { /* bitfield */
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RADEON_DOMAIN_GTT = 2,
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RADEON_DOMAIN_VRAM = 4,
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RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
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RADEON_DOMAIN_GDS = 8,
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RADEON_DOMAIN_OA = 16,
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};
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enum radeon_bo_flag { /* bitfield */
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RADEON_FLAG_GTT_WC = (1 << 0),
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RADEON_FLAG_CPU_ACCESS = (1 << 1),
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RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
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RADEON_FLAG_VIRTUAL = (1 << 3),
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RADEON_FLAG_VA_UNCACHED = (1 << 4),
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RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
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RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
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RADEON_FLAG_READ_ONLY = (1 << 7),
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RADEON_FLAG_32BIT = (1 << 8),
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RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
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RADEON_FLAG_ZERO_VRAM = (1 << 10),
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RADEON_FLAG_REPLAYABLE = (1 << 11),
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};
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enum radeon_ctx_priority {
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RADEON_CTX_PRIORITY_INVALID = -1,
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RADEON_CTX_PRIORITY_LOW = 0,
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RADEON_CTX_PRIORITY_MEDIUM,
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RADEON_CTX_PRIORITY_HIGH,
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RADEON_CTX_PRIORITY_REALTIME,
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};
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enum radeon_ctx_pstate {
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RADEON_CTX_PSTATE_NONE = 0,
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RADEON_CTX_PSTATE_STANDARD,
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RADEON_CTX_PSTATE_MIN_SCLK,
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RADEON_CTX_PSTATE_MIN_MCLK,
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RADEON_CTX_PSTATE_PEAK,
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};
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enum radeon_value_id {
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RADEON_ALLOCATED_VRAM,
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RADEON_ALLOCATED_VRAM_VIS,
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RADEON_ALLOCATED_GTT,
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RADEON_TIMESTAMP,
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RADEON_NUM_BYTES_MOVED,
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RADEON_NUM_EVICTIONS,
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RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
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RADEON_VRAM_USAGE,
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RADEON_VRAM_VIS_USAGE,
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RADEON_GTT_USAGE,
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RADEON_GPU_TEMPERATURE,
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RADEON_CURRENT_SCLK,
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RADEON_CURRENT_MCLK,
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};
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struct radeon_cmdbuf {
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unsigned cdw; /* Number of used dwords. */
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unsigned max_dw; /* Maximum number of dwords. */
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uint32_t *buf; /* The base pointer of the chunk. */
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};
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#define RADEON_SURF_TYPE_MASK 0xFF
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#define RADEON_SURF_TYPE_SHIFT 0
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#define RADEON_SURF_TYPE_1D 0
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#define RADEON_SURF_TYPE_2D 1
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#define RADEON_SURF_TYPE_3D 2
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#define RADEON_SURF_TYPE_CUBEMAP 3
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#define RADEON_SURF_TYPE_1D_ARRAY 4
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#define RADEON_SURF_TYPE_2D_ARRAY 5
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#define RADEON_SURF_MODE_MASK 0xFF
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#define RADEON_SURF_MODE_SHIFT 8
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#define RADEON_SURF_GET(v, field) \
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(((v) >> RADEON_SURF_##field##_SHIFT) & RADEON_SURF_##field##_MASK)
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#define RADEON_SURF_SET(v, field) (((v)&RADEON_SURF_##field##_MASK) << RADEON_SURF_##field##_SHIFT)
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#define RADEON_SURF_CLR(v, field) \
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((v) & ~(RADEON_SURF_##field##_MASK << RADEON_SURF_##field##_SHIFT))
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enum radeon_bo_layout {
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RADEON_LAYOUT_LINEAR = 0,
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RADEON_LAYOUT_TILED,
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RADEON_LAYOUT_SQUARETILED,
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RADEON_LAYOUT_UNKNOWN
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};
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/* Tiling info for display code, DRI sharing, and other data. */
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struct radeon_bo_metadata {
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/* Tiling flags describing the texture layout for display code
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* and DRI sharing.
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*/
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union {
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struct {
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enum radeon_bo_layout microtile;
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enum radeon_bo_layout macrotile;
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unsigned pipe_config;
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unsigned bankw;
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unsigned bankh;
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unsigned tile_split;
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unsigned mtilea;
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unsigned num_banks;
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unsigned stride;
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bool scanout;
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} legacy;
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struct {
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/* surface flags */
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unsigned swizzle_mode : 5;
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bool scanout;
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uint32_t dcc_offset_256b;
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uint32_t dcc_pitch_max;
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bool dcc_independent_64b_blocks;
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bool dcc_independent_128b_blocks;
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unsigned dcc_max_compressed_block_size;
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} gfx9;
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} u;
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/* Additional metadata associated with the buffer, in bytes.
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* The maximum size is 64 * 4. This is opaque for the winsys & kernel.
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* Supported by amdgpu only.
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*/
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uint32_t size_metadata;
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uint32_t metadata[64];
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};
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struct radeon_winsys_ctx;
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struct radeon_winsys_bo {
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uint64_t va;
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bool is_local;
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bool vram_no_cpu_access;
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bool use_global_list;
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enum radeon_bo_domain initial_domain;
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};
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struct radv_winsys_bo_list {
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struct radeon_winsys_bo **bos;
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unsigned count;
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};
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struct radv_winsys_submit_info {
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enum amd_ip_type ip_type;
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int queue_index;
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unsigned cs_count;
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struct radeon_cmdbuf **cs_array;
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struct radeon_cmdbuf *initial_preamble_cs;
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struct radeon_cmdbuf *continue_preamble_cs;
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};
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/* Kernel effectively allows 0-31. This sets some priorities for fixed
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* functionality buffers */
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enum {
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RADV_BO_PRIORITY_APPLICATION_MAX = 28,
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/* virtual buffers have 0 priority since the priority is not used. */
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RADV_BO_PRIORITY_VIRTUAL = 0,
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RADV_BO_PRIORITY_METADATA = 10,
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/* This should be considerably lower than most of the stuff below,
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* but how much lower is hard to say since we don't know application
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* assignments. Put it pretty high since it is GTT anyway. */
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RADV_BO_PRIORITY_QUERY_POOL = 29,
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RADV_BO_PRIORITY_DESCRIPTOR = 30,
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RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
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RADV_BO_PRIORITY_FENCE = 30,
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RADV_BO_PRIORITY_SHADER = 31,
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RADV_BO_PRIORITY_SCRATCH = 31,
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RADV_BO_PRIORITY_CS = 31,
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};
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struct radeon_winsys {
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void (*destroy)(struct radeon_winsys *ws);
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void (*query_info)(struct radeon_winsys *ws, struct radeon_info *info);
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uint64_t (*query_value)(struct radeon_winsys *ws, enum radeon_value_id value);
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bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,
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uint32_t *out);
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const char *(*get_chip_name)(struct radeon_winsys *ws);
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VkResult (*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment,
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enum radeon_bo_domain domain, enum radeon_bo_flag flags,
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unsigned priority, uint64_t address, struct radeon_winsys_bo **out_bo);
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void (*buffer_destroy)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo);
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void *(*buffer_map)(struct radeon_winsys_bo *bo);
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VkResult (*buffer_from_ptr)(struct radeon_winsys *ws, void *pointer, uint64_t size,
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unsigned priority, struct radeon_winsys_bo **out_bo);
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VkResult (*buffer_from_fd)(struct radeon_winsys *ws, int fd, unsigned priority,
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struct radeon_winsys_bo **out_bo, uint64_t *alloc_size);
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bool (*buffer_get_fd)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, int *fd);
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bool (*buffer_get_flags_from_fd)(struct radeon_winsys *ws, int fd,
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enum radeon_bo_domain *domains, enum radeon_bo_flag *flags);
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void (*buffer_unmap)(struct radeon_winsys_bo *bo);
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void (*buffer_set_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo,
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struct radeon_bo_metadata *md);
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void (*buffer_get_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo,
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struct radeon_bo_metadata *md);
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VkResult (*buffer_virtual_bind)(struct radeon_winsys *ws, struct radeon_winsys_bo *parent,
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uint64_t offset, uint64_t size, struct radeon_winsys_bo *bo,
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uint64_t bo_offset);
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VkResult (*buffer_make_resident)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo,
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bool resident);
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VkResult (*ctx_create)(struct radeon_winsys *ws, enum radeon_ctx_priority priority,
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struct radeon_winsys_ctx **ctx);
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void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
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bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum amd_ip_type amd_ip_type, int ring_index);
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int (*ctx_set_pstate)(struct radeon_winsys_ctx *ctx, uint32_t pstate);
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enum radeon_bo_domain (*cs_domain)(const struct radeon_winsys *ws);
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struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum amd_ip_type amd_ip_type);
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void (*cs_destroy)(struct radeon_cmdbuf *cs);
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void (*cs_reset)(struct radeon_cmdbuf *cs);
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VkResult (*cs_finalize)(struct radeon_cmdbuf *cs);
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void (*cs_grow)(struct radeon_cmdbuf *cs, size_t min_size);
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VkResult (*cs_submit)(struct radeon_winsys_ctx *ctx, uint32_t submit_count,
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const struct radv_winsys_submit_info *submits, uint32_t wait_count,
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const struct vk_sync_wait *waits, uint32_t signal_count,
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const struct vk_sync_signal *signals, bool can_patch);
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void (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo);
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void (*cs_add_buffers)(struct radeon_cmdbuf *to, struct radeon_cmdbuf *from);
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void (*cs_execute_secondary)(struct radeon_cmdbuf *parent, struct radeon_cmdbuf *child,
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bool allow_ib2);
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void (*cs_dump)(struct radeon_cmdbuf *cs, FILE *file, const int *trace_ids, int trace_id_count);
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void (*dump_bo_ranges)(struct radeon_winsys *ws, FILE *file);
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void (*dump_bo_log)(struct radeon_winsys *ws, FILE *file);
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int (*surface_init)(struct radeon_winsys *ws, const struct ac_surf_info *surf_info,
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struct radeon_surf *surf);
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int (*get_fd)(struct radeon_winsys *ws);
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const struct vk_sync_type *const *(*get_sync_types)(struct radeon_winsys *ws);
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};
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static inline void
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radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
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{
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cs->buf[cs->cdw++] = value;
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}
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static inline void
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radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values, unsigned count)
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{
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memcpy(cs->buf + cs->cdw, values, count * 4);
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cs->cdw += count;
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}
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static inline uint64_t
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radv_buffer_get_va(struct radeon_winsys_bo *bo)
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{
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return bo->va;
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}
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static inline void
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radv_cs_add_buffer(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo)
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{
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if (bo->use_global_list)
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return;
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ws->cs_add_buffer(cs, bo);
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}
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#endif /* RADV_RADEON_WINSYS_H */
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