304 lines
12 KiB
C
304 lines
12 KiB
C
/*
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* Copyright © 2021 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#define AC_SURFACE_INCLUDE_NIR
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#include "ac_surface.h"
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "vk_format.h"
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void
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radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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radv_DestroyPipeline(radv_device_to_handle(device), state->copy_vrs_htile_pipeline,
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&state->alloc);
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radv_DestroyPipelineLayout(radv_device_to_handle(device), state->copy_vrs_htile_p_layout,
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&state->alloc);
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), state->copy_vrs_htile_ds_layout,
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&state->alloc);
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}
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static nir_shader *
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build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf)
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{
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nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
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b.shader->info.workgroup_size[0] = 8;
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b.shader->info.workgroup_size[1] = 8;
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/* Get coordinates. */
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nir_ssa_def *global_id = get_global_ids(&b, 2);
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/* Multiply the coordinates by the HTILE block size. */
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nir_ssa_def *coord = nir_imul_imm(&b, global_id, 8);
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/* Load constants. */
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nir_ssa_def *constants = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range = 12);
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nir_ssa_def *htile_pitch = nir_channel(&b, constants, 0);
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nir_ssa_def *htile_slice_size = nir_channel(&b, constants, 1);
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nir_ssa_def *read_htile_value = nir_channel(&b, constants, 2);
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/* Get the HTILE addr from coordinates. */
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nir_ssa_def *zero = nir_imm_int(&b, 0);
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nir_ssa_def *htile_addr = ac_nir_htile_addr_from_coord(
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&b, &device->physical_device->rad_info, &surf->u.gfx9.zs.htile_equation, htile_pitch,
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htile_slice_size, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero);
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/* Set up the input VRS image descriptor. */
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const struct glsl_type *vrs_sampler_type =
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glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_FLOAT);
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nir_variable *input_vrs_img =
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nir_variable_create(b.shader, nir_var_uniform, vrs_sampler_type, "input_vrs_image");
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input_vrs_img->data.descriptor_set = 0;
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input_vrs_img->data.binding = 0;
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nir_ssa_def *input_vrs_img_deref = &nir_build_deref_var(&b, input_vrs_img)->dest.ssa;
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/* Load the VRS rates from the 2D image. */
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nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
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tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
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tex->op = nir_texop_txf;
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(global_id);
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tex->src[1].src_type = nir_tex_src_lod;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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tex->src[2].src_type = nir_tex_src_texture_deref;
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tex->src[2].src = nir_src_for_ssa(input_vrs_img_deref);
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tex->dest_type = nir_type_float32;
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tex->is_array = false;
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tex->coord_components = 2;
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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/* Extract the X/Y rates and clamp them because the maximum supported VRS rate is 2x2 (1x1 in
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* hardware).
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*
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* VRS rate X = min(value >> 2, 1)
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* VRS rate Y = min(value & 3, 1)
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*/
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nir_ssa_def *x_rate = nir_ushr_imm(&b, nir_channel(&b, &tex->dest.ssa, 0), 2);
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x_rate = nir_umin(&b, x_rate, nir_imm_int(&b, 1));
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nir_ssa_def *y_rate = nir_iand_imm(&b, nir_channel(&b, &tex->dest.ssa, 0), 3);
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y_rate = nir_umin(&b, y_rate, nir_imm_int(&b, 1));
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/* Compute the final VRS rate. */
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nir_ssa_def *vrs_rates = nir_ior(&b, nir_ishl_imm(&b, y_rate, 10), nir_ishl_imm(&b, x_rate, 6));
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/* Load the HTILE buffer descriptor. */
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nir_ssa_def *htile_buf = radv_meta_load_descriptor(&b, 0, 1);
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/* Load the HTILE value if requested, otherwise use the default value. */
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nir_variable *htile_value = nir_local_variable_create(b.impl, glsl_int_type(), "htile_value");
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nir_push_if(&b, nir_ieq_imm(&b, read_htile_value, 1));
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{
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/* Load the existing HTILE 32-bit value for this 8x8 pixels area. */
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nir_ssa_def *input_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr);
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/* Clear the 4-bit VRS rates. */
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nir_store_var(&b, htile_value, nir_iand_imm(&b, input_value, 0xfffff33f), 0x1);
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}
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nir_push_else(&b, NULL);
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{
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nir_store_var(&b, htile_value, nir_imm_int(&b, 0xfffff33f), 0x1);
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}
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nir_pop_if(&b, NULL);
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/* Set the VRS rates loaded from the image. */
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nir_ssa_def *output_value = nir_ior(&b, nir_load_var(&b, htile_value), vrs_rates);
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/* Store the updated HTILE 32-bit which contains the VRS rates. */
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nir_store_ssbo(&b, output_value, htile_buf, htile_addr, .access = ACCESS_NON_READABLE);
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return b.shader;
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}
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static VkResult
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radv_device_init_meta_copy_vrs_htile_state(struct radv_device *device,
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struct radeon_surf *surf)
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{
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struct radv_meta_state *state = &device->meta_state;
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nir_shader *cs = build_copy_vrs_htile_shader(device, surf);
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VkResult result;
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VkDescriptorSetLayoutCreateInfo ds_layout_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]){
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{.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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{.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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}};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_layout_info,
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&state->alloc, &state->copy_vrs_htile_ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineLayoutCreateInfo p_layout_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &state->copy_vrs_htile_ds_layout,
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.pushConstantRangeCount = 1,
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.pPushConstantRanges =
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&(VkPushConstantRange){
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VK_SHADER_STAGE_COMPUTE_BIT,
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0,
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12,
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},
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
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&state->copy_vrs_htile_p_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineShaderStageCreateInfo shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = shader_stage,
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.flags = 0,
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.layout = state->copy_vrs_htile_p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&state->cache), 1,
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&pipeline_info, NULL, &state->copy_vrs_htile_pipeline);
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fail:
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ralloc_free(cs);
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return result;
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}
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void
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radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image,
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VkExtent2D *extent, struct radv_image *dst_image,
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struct radv_buffer *htile_buffer, bool read_htile_value)
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{
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struct radv_device *device = cmd_buffer->device;
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struct radv_meta_state *state = &device->meta_state;
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struct radv_meta_saved_state saved_state;
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struct radv_image_view vrs_iview;
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assert(radv_image_has_htile(dst_image));
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if (!cmd_buffer->device->meta_state.copy_vrs_htile_pipeline) {
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VkResult ret = radv_device_init_meta_copy_vrs_htile_state(cmd_buffer->device,
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&dst_image->planes[0].surface);
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if (ret != VK_SUCCESS) {
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cmd_buffer->record_result = ret;
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return;
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}
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}
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cmd_buffer->state.flush_bits |=
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radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, NULL) |
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radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, NULL);
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radv_meta_save(
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&saved_state, cmd_buffer,
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RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
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state->copy_vrs_htile_pipeline);
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radv_image_view_init(&vrs_iview, cmd_buffer->device,
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&(VkImageViewCreateInfo){
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.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
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.image = radv_image_to_handle(vrs_image),
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.viewType = VK_IMAGE_VIEW_TYPE_2D,
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.format = vrs_image->vk.format,
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.subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
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.baseMipLevel = 0,
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.levelCount = 1,
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.baseArrayLayer = 0,
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.layerCount = 1},
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},
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0, NULL);
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radv_meta_push_descriptor_set(
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cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, state->copy_vrs_htile_p_layout, 0, /* set */
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2, /* descriptorWriteCount */
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(VkWriteDescriptorSet[]){
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{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.pImageInfo =
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(VkDescriptorImageInfo[]){
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{
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.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(&vrs_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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}},
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{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 1,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.pBufferInfo = &(VkDescriptorBufferInfo){.buffer = radv_buffer_to_handle(htile_buffer),
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.offset = 0,
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.range = htile_buffer->vk.size}}});
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const unsigned constants[3] = {
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dst_image->planes[0].surface.meta_pitch, dst_image->planes[0].surface.meta_slice_size,
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read_htile_value,
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};
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->copy_vrs_htile_p_layout,
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VK_SHADER_STAGE_COMPUTE_BIT, 0, 12, constants);
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uint32_t width = DIV_ROUND_UP(extent->width, 8);
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uint32_t height = DIV_ROUND_UP(extent->height, 8);
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radv_unaligned_dispatch(cmd_buffer, width, height, 1);
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radv_image_view_finish(&vrs_iview);
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radv_meta_restore(&saved_state, cmd_buffer);
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cmd_buffer->state.flush_bits |=
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RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
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radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
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}
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