222 lines
7.5 KiB
C
222 lines
7.5 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef RADV_CS_H
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#define RADV_CS_H
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#include <assert.h>
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#include <stdint.h>
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#include <string.h>
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#include "radv_private.h"
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#include "sid.h"
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static inline unsigned
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radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned needed)
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{
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if (cs->max_dw - cs->cdw < needed)
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ws->cs_grow(cs, needed);
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return cs->cdw + needed;
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}
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static inline void
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radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END);
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assert(cs->cdw + 2 + num <= cs->max_dw);
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assert(num);
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radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
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radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
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}
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static inline void
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radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_config_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void
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radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
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assert(cs->cdw + 2 + num <= cs->max_dw);
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assert(num);
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radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
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radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
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}
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static inline void
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radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_context_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void
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radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value)
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{
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assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
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assert(cs->cdw + 3 <= cs->max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
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radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
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radeon_emit(cs, value);
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}
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static inline void
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radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned mask)
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{
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assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
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assert(cs->cdw + 4 <= cs->max_dw);
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radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));
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radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
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radeon_emit(cs, mask);
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radeon_emit(cs, value);
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}
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static inline void
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radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
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assert(cs->cdw + 2 + num <= cs->max_dw);
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assert(num);
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radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
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radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
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}
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static inline void
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radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_sh_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void
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radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs,
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unsigned reg, unsigned idx, unsigned value)
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{
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assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
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assert(cs->cdw + 3 <= cs->max_dw);
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assert(idx);
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unsigned opcode = PKT3_SET_SH_REG_INDEX;
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if (pdevice->rad_info.gfx_level < GFX10)
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opcode = PKT3_SET_SH_REG;
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radeon_emit(cs, PKT3(opcode, 1, 0));
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radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));
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radeon_emit(cs, value);
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}
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static inline void
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gfx10_set_sh_reg_idx3(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
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assert(cs->cdw + 3 <= cs->max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_SH_REG_INDEX, 1, 0));
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radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (3 << 28));
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radeon_emit(cs, value);
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}
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static inline void
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radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
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assert(cs->cdw + 2 + num <= cs->max_dw);
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assert(num);
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radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
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radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
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}
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static inline void
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radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
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assert(cs->cdw + 2 + num <= cs->max_dw);
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assert(num);
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radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 1));
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radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
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}
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static inline void
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radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_uconfig_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void
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radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs,
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unsigned reg, unsigned idx, unsigned value)
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{
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assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
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assert(cs->cdw + 3 <= cs->max_dw);
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assert(idx);
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unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX;
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if (pdevice->rad_info.gfx_level < GFX9 ||
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(pdevice->rad_info.gfx_level == GFX9 && pdevice->rad_info.me_fw_version < 26))
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opcode = PKT3_SET_UCONFIG_REG;
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radeon_emit(cs, PKT3(opcode, 1, 0));
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radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
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radeon_emit(cs, value);
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}
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static inline void
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radeon_set_perfctr_reg(struct radv_cmd_buffer *cmd_buffer, unsigned reg, unsigned value)
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{
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
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assert(cs->cdw + 3 <= cs->max_dw);
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/*
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* On GFX10, there is a bug with the ME implementation of its content addressable memory (CAM),
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* that means that it can skip register writes due to not taking correctly into account the
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* fields from the GRBM_GFX_INDEX. With this bit we can force the write.
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*/
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bool filter_cam_workaround = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10 &&
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cmd_buffer->qf == RADV_QUEUE_GENERAL;
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radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0) | PKT3_RESET_FILTER_CAM(filter_cam_workaround));
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radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
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radeon_emit(cs, value);
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}
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static inline void
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radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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assert(reg < CIK_UCONFIG_REG_OFFSET);
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assert(cs->cdw + 6 <= cs->max_dw);
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radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
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radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_PERF));
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radeon_emit(cs, value);
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, reg >> 2);
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radeon_emit(cs, 0); /* unused */
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}
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#endif /* RADV_CS_H */
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