311 lines
11 KiB
C++
311 lines
11 KiB
C++
/*
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* Copyright © 2020 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "helpers.h"
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using namespace aco;
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BEGIN_TEST(assembler.s_memtime)
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for (unsigned i = GFX6; i <= GFX10; i++) {
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if (!setup_cs(NULL, (amd_gfx_level)i))
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continue;
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//~gfx[6-7]>> c7800000
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//~gfx[6-7]! bf810000
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//~gfx[8-9]>> s_memtime s[0:1] ; c0900000 00000000
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//~gfx10>> s_memtime s[0:1] ; f4900000 fa000000
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bld.smem(aco_opcode::s_memtime, bld.def(s2)).def(0).setFixed(PhysReg{0});
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finish_assembler_test();
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}
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END_TEST
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BEGIN_TEST(assembler.branch_3f)
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if (!setup_cs(NULL, (amd_gfx_level)GFX10))
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return;
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//! BB0:
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//! s_branch BB1 ; bf820040
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//! s_nop 0 ; bf800000
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bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1);
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for (unsigned i = 0; i < 0x3f; i++)
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bld.vop1(aco_opcode::v_nop);
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bld.reset(program->create_and_insert_block());
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program->blocks[1].linear_preds.push_back(0u);
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finish_assembler_test();
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END_TEST
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BEGIN_TEST(assembler.long_jump.unconditional_forwards)
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if (!setup_cs(NULL, (amd_gfx_level)GFX10))
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return;
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//!BB0:
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//! s_getpc_b64 s[0:1] ; be801f00
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//! s_addc_u32 s0, s0, 0x20014 ; 8200ff00 00020014
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//! s_bitcmp1_b32 s0, 0 ; bf0d8000
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//! s_bitset0_b32 s0, 0 ; be801b80
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//! s_setpc_b64 s[0:1] ; be802000
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bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
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bld.reset(program->create_and_insert_block());
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//! s_nop 0 ; bf800000
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//!(then repeated 32767 times)
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for (unsigned i = 0; i < INT16_MAX + 1; i++)
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bld.sopp(aco_opcode::s_nop, -1, 0);
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//! BB2:
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//! s_endpgm ; bf810000
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bld.reset(program->create_and_insert_block());
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program->blocks[2].linear_preds.push_back(0u);
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program->blocks[2].linear_preds.push_back(1u);
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finish_assembler_test();
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END_TEST
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BEGIN_TEST(assembler.long_jump.conditional_forwards)
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if (!setup_cs(NULL, (amd_gfx_level)GFX10))
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return;
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//! BB0:
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//! s_cbranch_scc1 BB1 ; bf850006
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//! s_getpc_b64 s[0:1] ; be801f00
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//! s_addc_u32 s0, s0, 0x20014 ; 8200ff00 00020014
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//! s_bitcmp1_b32 s0, 0 ; bf0d8000
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//! s_bitset0_b32 s0, 0 ; be801b80
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//! s_setpc_b64 s[0:1] ; be802000
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bld.sopp(aco_opcode::s_cbranch_scc0, Definition(PhysReg(0), s2), 2);
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bld.reset(program->create_and_insert_block());
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//! BB1:
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//! s_nop 0 ; bf800000
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//!(then repeated 32767 times)
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for (unsigned i = 0; i < INT16_MAX + 1; i++)
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bld.sopp(aco_opcode::s_nop, -1, 0);
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//! BB2:
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//! s_endpgm ; bf810000
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bld.reset(program->create_and_insert_block());
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program->blocks[1].linear_preds.push_back(0u);
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program->blocks[2].linear_preds.push_back(0u);
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program->blocks[2].linear_preds.push_back(1u);
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finish_assembler_test();
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END_TEST
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BEGIN_TEST(assembler.long_jump.unconditional_backwards)
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if (!setup_cs(NULL, (amd_gfx_level)GFX10))
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return;
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//!BB0:
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//! s_nop 0 ; bf800000
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//!(then repeated 32767 times)
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for (unsigned i = 0; i < INT16_MAX + 1; i++)
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bld.sopp(aco_opcode::s_nop, -1, 0);
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//! s_getpc_b64 s[0:1] ; be801f00
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//! s_addc_u32 s0, s0, 0xfffdfffc ; 8200ff00 fffdfffc
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//! s_bitcmp1_b32 s0, 0 ; bf0d8000
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//! s_bitset0_b32 s0, 0 ; be801b80
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//! s_setpc_b64 s[0:1] ; be802000
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bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 0);
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//! BB1:
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//! s_endpgm ; bf810000
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bld.reset(program->create_and_insert_block());
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program->blocks[0].linear_preds.push_back(0u);
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program->blocks[1].linear_preds.push_back(0u);
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finish_assembler_test();
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END_TEST
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BEGIN_TEST(assembler.long_jump.conditional_backwards)
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if (!setup_cs(NULL, (amd_gfx_level)GFX10))
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return;
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//!BB0:
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//! s_nop 0 ; bf800000
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//!(then repeated 32767 times)
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for (unsigned i = 0; i < INT16_MAX + 1; i++)
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bld.sopp(aco_opcode::s_nop, -1, 0);
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//! s_cbranch_execz BB1 ; bf880006
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//! s_getpc_b64 s[0:1] ; be801f00
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//! s_addc_u32 s0, s0, 0xfffdfff8 ; 8200ff00 fffdfff8
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//! s_bitcmp1_b32 s0, 0 ; bf0d8000
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//! s_bitset0_b32 s0, 0 ; be801b80
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//! s_setpc_b64 s[0:1] ; be802000
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bld.sopp(aco_opcode::s_cbranch_execnz, Definition(PhysReg(0), s2), 0);
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//! BB1:
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//! s_endpgm ; bf810000
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bld.reset(program->create_and_insert_block());
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program->blocks[0].linear_preds.push_back(0u);
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program->blocks[1].linear_preds.push_back(0u);
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finish_assembler_test();
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END_TEST
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BEGIN_TEST(assembler.long_jump.3f)
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if (!setup_cs(NULL, (amd_gfx_level)GFX10))
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return;
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//! BB0:
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//! s_branch BB1 ; bf820040
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//! s_nop 0 ; bf800000
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bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1);
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for (unsigned i = 0; i < 0x3f - 6; i++) // a unconditional long jump is 6 dwords
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bld.vop1(aco_opcode::v_nop);
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bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
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bld.reset(program->create_and_insert_block());
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for (unsigned i = 0; i < INT16_MAX + 1; i++)
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bld.vop1(aco_opcode::v_nop);
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bld.reset(program->create_and_insert_block());
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program->blocks[1].linear_preds.push_back(0u);
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program->blocks[2].linear_preds.push_back(0u);
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program->blocks[2].linear_preds.push_back(1u);
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finish_assembler_test();
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END_TEST
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BEGIN_TEST(assembler.long_jump.constaddr)
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if (!setup_cs(NULL, (amd_gfx_level)GFX10))
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return;
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//>> s_getpc_b64 s[0:1] ; be801f00
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bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
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bld.reset(program->create_and_insert_block());
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for (unsigned i = 0; i < INT16_MAX + 1; i++)
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bld.sopp(aco_opcode::s_nop, -1, 0);
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bld.reset(program->create_and_insert_block());
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//>> s_getpc_b64 s[0:1] ; be801f00
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//! s_add_u32 s0, s0, 0xe4 ; 8000ff00 000000e4
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bld.sop1(aco_opcode::p_constaddr_getpc, Definition(PhysReg(0), s2), Operand::zero());
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bld.sop2(aco_opcode::p_constaddr_addlo, Definition(PhysReg(0), s1), bld.def(s1, scc),
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Operand(PhysReg(0), s1), Operand::zero(), Operand::zero());
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program->blocks[2].linear_preds.push_back(0u);
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program->blocks[2].linear_preds.push_back(1u);
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finish_assembler_test();
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END_TEST
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BEGIN_TEST(assembler.v_add3)
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for (unsigned i = GFX9; i <= GFX10; i++) {
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if (!setup_cs(NULL, (amd_gfx_level)i))
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continue;
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//~gfx9>> v_add3_u32 v0, 0, 0, 0 ; d1ff0000 02010080
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//~gfx10>> v_add3_u32 v0, 0, 0, 0 ; d76d0000 02010080
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aco_ptr<VOP3_instruction> add3{create_instruction<VOP3_instruction>(aco_opcode::v_add3_u32, Format::VOP3, 3, 1)};
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add3->operands[0] = Operand::zero();
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add3->operands[1] = Operand::zero();
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add3->operands[2] = Operand::zero();
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add3->definitions[0] = Definition(PhysReg(0), v1);
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bld.insert(std::move(add3));
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finish_assembler_test();
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}
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END_TEST
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BEGIN_TEST(assembler.v_add3_clamp)
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for (unsigned i = GFX9; i <= GFX10; i++) {
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if (!setup_cs(NULL, (amd_gfx_level)i))
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continue;
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//~gfx9>> integer addition + clamp ; d1ff8000 02010080
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//~gfx10>> integer addition + clamp ; d76d8000 02010080
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aco_ptr<VOP3_instruction> add3{create_instruction<VOP3_instruction>(aco_opcode::v_add3_u32, Format::VOP3, 3, 1)};
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add3->operands[0] = Operand::zero();
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add3->operands[1] = Operand::zero();
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add3->operands[2] = Operand::zero();
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add3->definitions[0] = Definition(PhysReg(0), v1);
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add3->clamp = 1;
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bld.insert(std::move(add3));
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finish_assembler_test();
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}
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END_TEST
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BEGIN_TEST(assembler.smem_offset)
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for (unsigned i = GFX9; i <= GFX10; i++) {
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if (!setup_cs(NULL, (amd_gfx_level)i))
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continue;
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Definition dst(PhysReg(7), s1);
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Operand sbase(PhysReg(6), s2);
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Operand offset(PhysReg(5), s1);
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//~gfx9>> s_load_dword s7, s[6:7], s5 ; c00001c3 00000005
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//~gfx10>> s_load_dword s7, s[6:7], s5 ; f40001c3 0a000000
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bld.smem(aco_opcode::s_load_dword, dst, sbase, offset);
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//~gfx9! s_load_dword s7, s[6:7], 0x42 ; c00201c3 00000042
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//~gfx10! s_load_dword s7, s[6:7], 0x42 ; f40001c3 fa000042
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bld.smem(aco_opcode::s_load_dword, dst, sbase, Operand::c32(0x42));
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if (i >= GFX9) {
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//~gfx9! s_load_dword s7, s[6:7], s5 offset:0x42 ; c00241c3 0a000042
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//~gfx10! s_load_dword s7, s[6:7], s5 offset:0x42 ; f40001c3 0a000042
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bld.smem(aco_opcode::s_load_dword, dst, sbase, Operand::c32(0x42), offset);
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}
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finish_assembler_test();
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}
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END_TEST
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BEGIN_TEST(assembler.p_constaddr)
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if (!setup_cs(NULL, GFX9))
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return;
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Definition dst0 = bld.def(s2);
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Definition dst1 = bld.def(s2);
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dst0.setFixed(PhysReg(0));
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dst1.setFixed(PhysReg(2));
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//>> s_getpc_b64 s[0:1] ; be801c00
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//! s_add_u32 s0, s0, 24 ; 8000ff00 00000018
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bld.pseudo(aco_opcode::p_constaddr, dst0, Operand::zero());
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//! s_getpc_b64 s[2:3] ; be821c00
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//! s_add_u32 s2, s2, 44 ; 8002ff02 0000002c
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bld.pseudo(aco_opcode::p_constaddr, dst1, Operand::c32(32));
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aco::lower_to_hw_instr(program.get());
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finish_assembler_test();
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END_TEST
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