226 lines
7.0 KiB
C
226 lines
7.0 KiB
C
/*
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* Copyright © 2021 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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#ifndef AC_SURFACE_TEST_COMMON_H
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#define AC_SURFACE_TEST_COMMON_H
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#include "ac_gpu_info.h"
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#include "amdgfxregs.h"
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typedef void (*gpu_init_func)(struct radeon_info *info);
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static void init_vega10(struct radeon_info *info)
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{
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info->family = CHIP_VEGA10;
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info->gfx_level = GFX9;
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info->family_id = AMDGPU_FAMILY_AI;
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info->chip_external_rev = 0x01;
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info->use_display_dcc_unaligned = false;
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info->use_display_dcc_with_retile_blit = false;
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info->has_graphics = true;
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info->tcc_cache_line_size = 64;
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info->max_render_backends = 16;
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info->gb_addr_config = 0x2a114042;
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}
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static void init_vega20(struct radeon_info *info)
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{
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info->family = CHIP_VEGA20;
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info->gfx_level = GFX9;
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info->family_id = AMDGPU_FAMILY_AI;
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info->chip_external_rev = 0x30;
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info->use_display_dcc_unaligned = false;
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info->use_display_dcc_with_retile_blit = false;
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info->has_graphics = true;
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info->tcc_cache_line_size = 64;
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info->max_render_backends = 16;
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info->gb_addr_config = 0x2a114042;
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}
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static void init_raven(struct radeon_info *info)
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{
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info->family = CHIP_RAVEN;
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info->gfx_level = GFX9;
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info->family_id = AMDGPU_FAMILY_RV;
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info->chip_external_rev = 0x01;
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info->use_display_dcc_unaligned = false;
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info->use_display_dcc_with_retile_blit = true;
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info->has_graphics = true;
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info->tcc_cache_line_size = 64;
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info->max_render_backends = 2;
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info->gb_addr_config = 0x24000042;
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}
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static void init_raven2(struct radeon_info *info)
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{
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info->family = CHIP_RAVEN2;
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info->gfx_level = GFX9;
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info->family_id = AMDGPU_FAMILY_RV;
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info->chip_external_rev = 0x82;
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info->use_display_dcc_unaligned = true;
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info->use_display_dcc_with_retile_blit = false;
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info->has_graphics = true;
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info->tcc_cache_line_size = 64;
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info->max_render_backends = 1;
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info->gb_addr_config = 0x26013041;
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}
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static void init_navi10(struct radeon_info *info)
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{
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info->family = CHIP_NAVI10;
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info->gfx_level = GFX10;
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info->family_id = AMDGPU_FAMILY_NV;
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info->chip_external_rev = 3;
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info->use_display_dcc_unaligned = false;
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info->use_display_dcc_with_retile_blit = false;
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info->has_graphics = true;
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info->tcc_cache_line_size = 128;
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info->gb_addr_config = 0x00100044;
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}
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static void init_navi14(struct radeon_info *info)
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{
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info->family = CHIP_NAVI14;
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info->gfx_level = GFX10;
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info->family_id = AMDGPU_FAMILY_NV;
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info->chip_external_rev = 0x15;
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info->use_display_dcc_unaligned = false;
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info->use_display_dcc_with_retile_blit = false;
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info->has_graphics = true;
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info->tcc_cache_line_size = 128;
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info->gb_addr_config = 0x00000043;
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}
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static void init_gfx103(struct radeon_info *info)
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{
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info->family = CHIP_NAVI21; /* This doesn't affect tests. */
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info->gfx_level = GFX10_3;
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info->family_id = AMDGPU_FAMILY_NV;
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info->chip_external_rev = 0x28;
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info->use_display_dcc_unaligned = false;
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info->use_display_dcc_with_retile_blit = true;
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info->has_graphics = true;
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info->tcc_cache_line_size = 128;
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info->has_rbplus = true;
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info->rbplus_allowed = true;
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info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
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}
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static void init_gfx11(struct radeon_info *info)
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{
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info->family = CHIP_UNKNOWN;
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info->gfx_level = GFX11;
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info->family_id = 0x00;
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info->chip_external_rev = 0x01;
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info->use_display_dcc_unaligned = false;
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info->use_display_dcc_with_retile_blit = true;
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info->has_graphics = true;
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info->tcc_cache_line_size = 128;
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info->has_rbplus = true;
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info->rbplus_allowed = true;
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info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
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}
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struct testcase {
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const char *name;
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gpu_init_func init;
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int banks_or_pkrs;
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int pipes;
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int se;
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int rb_per_se;
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};
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static struct testcase testcases[] = {
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{"vega10", init_vega10, 4, 2, 2, 2},
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{"vega10_diff_bank", init_vega10, 3, 2, 2, 2},
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{"vega10_diff_rb", init_vega10, 4, 2, 2, 0},
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{"vega10_diff_pipe", init_vega10, 4, 0, 2, 2},
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{"vega10_diff_se", init_vega10, 4, 2, 1, 2},
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{"vega20", init_vega20, 4, 2, 2, 2},
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{"raven", init_raven, 0, 2, 0, 1},
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{"raven2", init_raven2, 3, 1, 0, 1},
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/* Just test a bunch of different numbers. (packers, pipes) */
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{"navi10", init_navi10, 0, 4},
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{"navi10_diff_pipe", init_navi10, 0, 3},
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{"navi10_diff_pkr", init_navi10, 1, 4},
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{"navi14", init_navi14, 1, 3},
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{"gfx103_16pipe", init_gfx103, 4, 4},
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{"gfx103_16pipe_8pkr", init_gfx103, 3, 4},
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{"gfx103_8pipe", init_gfx103, 3, 3},
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{"gfx103_4pipe", init_gfx103, 2, 2},
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{"gfx103_4pipe_2pkr", init_gfx103, 1, 2},
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};
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static struct radeon_info get_radeon_info(struct testcase *testcase)
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{
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struct radeon_info info = {
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.drm_major = 3,
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.drm_minor = 30,
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};
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testcase->init(&info);
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switch(info.gfx_level) {
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case GFX9:
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info.gb_addr_config = (info.gb_addr_config &
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C_0098F8_NUM_PIPES &
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C_0098F8_NUM_BANKS &
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C_0098F8_NUM_SHADER_ENGINES_GFX9 &
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C_0098F8_NUM_RB_PER_SE) |
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S_0098F8_NUM_PIPES(testcase->pipes) |
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S_0098F8_NUM_BANKS(testcase->banks_or_pkrs) |
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S_0098F8_NUM_SHADER_ENGINES_GFX9(testcase->se) |
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S_0098F8_NUM_RB_PER_SE(testcase->rb_per_se);
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break;
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case GFX10:
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case GFX10_3:
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case GFX11:
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info.gb_addr_config = (info.gb_addr_config &
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C_0098F8_NUM_PIPES &
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C_0098F8_NUM_PKRS) |
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S_0098F8_NUM_PIPES(testcase->pipes) |
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S_0098F8_NUM_PKRS(testcase->banks_or_pkrs);
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/* 1 packer implies 1 RB except gfx10 where the field is ignored. */
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info.max_render_backends = info.gfx_level == GFX10 || testcase->banks_or_pkrs ? 2 : 1;
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break;
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default:
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unreachable("Unhandled generation");
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}
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return info;
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}
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#endif
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