435 lines
14 KiB
C
435 lines
14 KiB
C
/* Make the test not meaningless when asserts are disabled. */
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#undef NDEBUG
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#include <assert.h>
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <amdgpu.h>
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#include "drm-uapi/amdgpu_drm.h"
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#include "drm-uapi/drm_fourcc.h"
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#include "ac_surface.h"
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#include "util/macros.h"
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#include "util/u_math.h"
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#include "util/u_vector.h"
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#include "util/mesa-sha1.h"
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#include "addrlib/inc/addrinterface.h"
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#include "ac_surface_test_common.h"
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/*
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* The main goal of this test is making sure that we do
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* not change the meaning of existing modifiers.
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*/
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struct test_entry {
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/* key part */
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uint64_t modifier;
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unsigned w;
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unsigned h;
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enum pipe_format format;
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/* debug info */
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const char *name;
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uint8_t pipes;
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uint8_t rb;
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uint8_t banks_or_pkrs;
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uint8_t se;
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/* value to determine uniqueness */
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unsigned char hash[20];
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/* u_vector requires power of two sizing */
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char padding[sizeof(void*) == 8 ? 8 : 16];
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};
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static uint64_t
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block_count(unsigned w, unsigned h, unsigned elem_bits, unsigned block_bits,
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unsigned *aligned_pitch, unsigned *aligned_height)
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{
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unsigned align_bits = block_bits - elem_bits;
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unsigned w_align = 1 << (align_bits / 2 + align_bits % 2);
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unsigned h_align = 1 << (align_bits / 2);
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w = align(w, w_align);
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h = align(h, h_align);
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if (aligned_pitch)
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*aligned_pitch = w;
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if (aligned_height)
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*aligned_height = h;
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return ((uint64_t)w * h) >> align_bits;
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}
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static ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
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get_addr_from_coord_base(ADDR_HANDLE addrlib, const struct radeon_surf *surf,
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unsigned w, unsigned h, enum pipe_format format,
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bool rb_aligned, bool pipe_aligned)
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{
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ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
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ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
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din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
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dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
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din.swizzleMode = surf->u.gfx9.swizzle_mode;
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din.resourceType = ADDR_RSRC_TEX_2D;
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din.bpp = util_format_get_blocksizebits(format);
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din.unalignedWidth = w;
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din.unalignedHeight = h;
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din.numSlices = 1;
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din.numMipLevels = 1;
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din.numFrags = 1;
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din.dccKeyFlags.pipeAligned = surf->u.gfx9.color.dcc.pipe_aligned;
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din.dccKeyFlags.rbAligned = surf->u.gfx9.color.dcc.rb_aligned;
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din.dataSurfaceSize = surf->surf_size;
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ADDR_E_RETURNCODE ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
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assert(ret == ADDR_OK);
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT dcc_input = {0};
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dcc_input.size = sizeof(dcc_input);
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dcc_input.swizzleMode = surf->u.gfx9.swizzle_mode;
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dcc_input.resourceType = ADDR_RSRC_TEX_2D;
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dcc_input.bpp = din.bpp;
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dcc_input.numSlices = 1;
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dcc_input.numMipLevels = 1;
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dcc_input.numFrags = 1;
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dcc_input.dccKeyFlags.pipeAligned = pipe_aligned;
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dcc_input.dccKeyFlags.rbAligned = rb_aligned;
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dcc_input.pitch = dout.pitch;
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dcc_input.height = dout.height;
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dcc_input.compressBlkWidth = dout.compressBlkWidth;
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dcc_input.compressBlkHeight = dout.compressBlkHeight;
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dcc_input.compressBlkDepth = dout.compressBlkDepth;
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dcc_input.metaBlkWidth = dout.metaBlkWidth;
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dcc_input.metaBlkHeight = dout.metaBlkHeight;
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dcc_input.metaBlkDepth = dout.metaBlkDepth;
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return dcc_input;
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}
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static
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void generate_hash(struct ac_addrlib *ac_addrlib,
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struct test_entry *entry,
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const struct radeon_surf *surf)
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{
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ADDR_HANDLE addrlib = ac_addrlib_get_handle(ac_addrlib);
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srandom(53);
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struct mesa_sha1 ctx;
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_mesa_sha1_init(&ctx);
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_mesa_sha1_update(&ctx, &surf->total_size, sizeof(surf->total_size));
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_mesa_sha1_update(&ctx, &surf->meta_offset, sizeof(surf->meta_offset));
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_mesa_sha1_update(&ctx, &surf->display_dcc_offset, sizeof(surf->display_dcc_offset));
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_mesa_sha1_update(&ctx, &surf->u.gfx9.color.display_dcc_pitch_max,
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sizeof(surf->u.gfx9.color.display_dcc_pitch_max));
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ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT input = {0};
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input.size = sizeof(input);
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input.swizzleMode = surf->u.gfx9.swizzle_mode;
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input.resourceType = ADDR_RSRC_TEX_2D;
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input.bpp = util_format_get_blocksizebits(entry->format);
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input.unalignedWidth = entry->w;
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input.unalignedHeight = entry->h;
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input.numSlices = 1;
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input.numMipLevels = 1;
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input.numSamples = 1;
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input.numFrags = 1;
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input.pitchInElement = surf->u.gfx9.surf_pitch;
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT dcc_input = {0};
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if (surf->meta_offset) {
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dcc_input = get_addr_from_coord_base(addrlib, surf, entry->w,
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entry->h, entry->format,
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surf->u.gfx9.color.dcc.rb_aligned,
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surf->u.gfx9.color.dcc.pipe_aligned);
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}
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT display_dcc_input = {0};
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if (surf->display_dcc_offset) {
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display_dcc_input = get_addr_from_coord_base(addrlib, surf, entry->w,
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entry->h, entry->format,
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false, false);
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}
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for (unsigned i = 0; i < 1000; ++i) {
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int32_t x, y;
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x = random();
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y = random();
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input.x = (x & INT_MAX) % entry->w;
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input.y = (y & INT_MAX) % entry->h;
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ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT output = {0};
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output.size = sizeof(output);
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ADDR_E_RETURNCODE ret = Addr2ComputeSurfaceAddrFromCoord(addrlib, &input, &output);
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assert(ret == ADDR_OK);
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_mesa_sha1_update(&ctx, &output.addr, sizeof(output.addr));
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if (surf->meta_offset) {
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dcc_input.x = (x & INT_MAX) % entry->w;
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dcc_input.y = (y & INT_MAX) % entry->h;
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT dcc_output = {0};
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dcc_output.size = sizeof(dcc_output);
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ret = Addr2ComputeDccAddrFromCoord(addrlib, &dcc_input, &dcc_output);
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assert(ret == ADDR_OK);
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_mesa_sha1_update(&ctx, &dcc_output.addr, sizeof(dcc_output.addr));
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}
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if (surf->display_dcc_offset) {
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display_dcc_input.x = (x & INT_MAX) % entry->w;
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display_dcc_input.y = (y & INT_MAX) % entry->h;
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT dcc_output = {0};
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dcc_output.size = sizeof(dcc_output);
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ret = Addr2ComputeDccAddrFromCoord(addrlib, &display_dcc_input, &dcc_output);
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assert(ret == ADDR_OK);
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_mesa_sha1_update(&ctx, &dcc_output.addr, sizeof(dcc_output.addr));
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}
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}
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_mesa_sha1_final(&ctx, entry->hash);
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}
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static void test_modifier(const struct radeon_info *info,
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const char *name,
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struct ac_addrlib *addrlib,
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uint64_t modifier,
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enum pipe_format format,
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struct u_vector *test_entries)
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{
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unsigned elem_bits = util_logbase2(util_format_get_blocksize(format));
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const unsigned dims[][2] = {
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{1, 1},
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{1920, 1080},
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{1366, 768},
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{3840, 2160},
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{233, 938},
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};
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for (unsigned i = 0; i < ARRAY_SIZE(dims); ++i) {
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struct ac_surf_config config = (struct ac_surf_config) {
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.info = (struct ac_surf_info) {
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.width = dims[i][0],
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.height = dims[i][1],
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.depth = 1,
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.samples = 1,
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.storage_samples = 1,
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.levels = 1,
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.num_channels = 3,
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.array_size = 1
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},
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};
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struct test_entry entry = {
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.modifier = modifier,
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.w = config.info.width,
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.h = config.info.height,
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.format = format,
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.name = name,
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.pipes = G_0098F8_NUM_PIPES(info->gb_addr_config),
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.rb = G_0098F8_NUM_RB_PER_SE(info->gb_addr_config) +
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G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config),
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.se = G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config),
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.banks_or_pkrs = info->gfx_level >= GFX10 ?
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G_0098F8_NUM_PKRS(info->gb_addr_config) : G_0098F8_NUM_BANKS(info->gb_addr_config)
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};
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struct radeon_surf surf = (struct radeon_surf) {
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.blk_w = 1,
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.blk_h = 1,
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.bpe = util_format_get_blocksize(format),
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.modifier = modifier,
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};
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int r = ac_compute_surface(addrlib, info, &config, RADEON_SURF_MODE_2D, &surf);
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assert(!r);
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assert(surf.cmask_offset == 0);
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assert(surf.fmask_offset == 0);
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unsigned block_size_bits = surf.u.gfx9.swizzle_mode >= ADDR_SW_256KB_Z_X ? 18 : 16;
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uint64_t surf_size;
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unsigned aligned_pitch, aligned_height;
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if (modifier != DRM_FORMAT_MOD_LINEAR) {
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surf_size = block_count(dims[i][0], dims[i][1],
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elem_bits, block_size_bits, &aligned_pitch,
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&aligned_height) << block_size_bits;
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} else {
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aligned_pitch = align(dims[i][0], 256 / util_format_get_blocksize(format));
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aligned_height = dims[i][1];
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surf_size = align(dims[i][0] * util_format_get_blocksize(format), 256) * dims[i][1];
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}
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assert(surf.u.gfx9.surf_pitch == aligned_pitch);
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assert(surf.u.gfx9.surf_height == aligned_height);
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assert(surf.surf_size == surf_size);
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uint64_t expected_offset = surf_size;
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if (ac_modifier_has_dcc_retile(modifier)) {
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unsigned dcc_align = info->gfx_level >= GFX10 ? 4096 : 65536;
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unsigned dcc_pitch;
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uint64_t dcc_size = block_count(dims[i][0], dims[i][1],
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elem_bits, 20, &dcc_pitch,
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NULL) << 12;
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assert(surf.u.gfx9.color.display_dcc_size == align(dcc_size, dcc_align));
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assert(surf.u.gfx9.color.display_dcc_pitch_max + 1 == dcc_pitch);
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assert(surf.display_dcc_offset == expected_offset);
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expected_offset += align(dcc_size, dcc_align);
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} else
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assert(!surf.display_dcc_offset);
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if (ac_modifier_has_dcc(modifier)) {
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uint64_t dcc_align = 1;
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unsigned block_bits;
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if (info->gfx_level >= GFX10) {
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unsigned num_pipes = G_0098F8_NUM_PIPES(info->gb_addr_config);
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if (info->gfx_level >= GFX10_3 &&
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G_0098F8_NUM_PKRS(info->gb_addr_config) == num_pipes && num_pipes > 1)
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++num_pipes;
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block_bits = 16 +
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num_pipes +
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G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
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block_bits = MAX2(block_bits, 20);
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dcc_align = MAX2(4096, 256 <<
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(num_pipes +
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G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config)));
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} else {
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block_bits = 18 +
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G_0098F8_NUM_RB_PER_SE(info->gb_addr_config) +
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G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config);
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block_bits = MAX2(block_bits, 20);
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dcc_align = 65536;
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}
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expected_offset = align(expected_offset, dcc_align);
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assert(surf.meta_offset == expected_offset);
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uint64_t dcc_size = block_count(dims[i][0], dims[i][1],
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elem_bits, block_bits,
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NULL, NULL) << (block_bits - 8);
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dcc_size = align64(dcc_size, dcc_align);
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assert(surf.meta_size == dcc_size);
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expected_offset += dcc_size;
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} else
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assert(!surf.meta_offset);
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assert(surf.total_size == expected_offset);
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generate_hash(addrlib, &entry, &surf);
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*(struct test_entry*)u_vector_add(test_entries) = entry;
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}
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}
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static void run_modifier_test(struct u_vector *test_entries, const char *name,
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const struct radeon_info *info)
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{
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struct ac_addrlib *addrlib = ac_addrlib_create(info, NULL);
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assert(addrlib);
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const struct ac_modifier_options options = {
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.dcc = true,
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.dcc_retile = true,
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};
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enum pipe_format formats[] = {
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PIPE_FORMAT_R8_UNORM,
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PIPE_FORMAT_R16_UNORM,
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PIPE_FORMAT_R32_FLOAT,
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PIPE_FORMAT_R32G32_FLOAT,
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PIPE_FORMAT_R32G32B32A32_FLOAT
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};
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for (unsigned j = 0; j < ARRAY_SIZE(formats); ++j) {
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unsigned mod_count = 0;
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ac_get_supported_modifiers(info, &options, formats[j], &mod_count, NULL);
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uint64_t *modifiers = malloc(sizeof(uint64_t) * mod_count);
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ac_get_supported_modifiers(info, &options, formats[j], &mod_count, modifiers);
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for (unsigned i = 0; i < mod_count; ++i) {
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test_modifier(info, name, addrlib, modifiers[i], formats[j], test_entries);
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}
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free(modifiers);
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}
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ac_addrlib_destroy(addrlib);
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}
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static int compare_test_entry(const void *a, const void *b)
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{
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return memcmp(a, b, sizeof(struct test_entry));
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}
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static bool test_entry_key_equal(const struct test_entry *a, const struct test_entry *b)
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{
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return a->modifier == b->modifier && a->w == b->w && a->h == b->h && a->format == b->format;
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}
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static bool test_entry_value_equal(const struct test_entry *a, const struct test_entry *b)
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{
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if (memcmp(a->hash, b->hash, sizeof(a->hash)))
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return false;
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return true;
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}
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static void print_test_entry(const struct test_entry *e)
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{
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printf("%.16" PRIx64 " %.4d %.4d %.2d %s %d %d %d %d\n", e->modifier, e->w, e->h,
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util_format_get_blocksize(e->format), e->name, e->pipes, e->rb, e->se, e->banks_or_pkrs);
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}
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int main()
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{
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STATIC_ASSERT(sizeof(struct test_entry) == 64);
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struct u_vector test_entries;
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u_vector_init_pow2(&test_entries, 64, sizeof(struct test_entry));
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for (unsigned i = 0; i < ARRAY_SIZE(testcases); ++i) {
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struct radeon_info info = get_radeon_info(&testcases[i]);
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run_modifier_test(&test_entries, testcases[i].name, &info);
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}
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qsort(u_vector_tail(&test_entries),
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u_vector_length(&test_entries),
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sizeof(struct test_entry),
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compare_test_entry);
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struct test_entry *cur, *prev = NULL, *prevprev = NULL;
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bool mismatched_duplicates = false;
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u_vector_foreach(cur, &test_entries) {
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if (prev && test_entry_key_equal(cur, prev) &&
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!test_entry_value_equal(cur, prev)) {
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if (!prevprev || !test_entry_key_equal(prev, prevprev)) {
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print_test_entry(prev);
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}
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print_test_entry(cur);
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mismatched_duplicates = true;
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}
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prevprev = prev;
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prev = cur;
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}
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assert(!mismatched_duplicates);
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u_vector_finish(&test_entries);
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return 0;
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}
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