144 lines
5.3 KiB
C
144 lines
5.3 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "ac_binary.h"
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#include "ac_gpu_info.h"
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#include "util/u_math.h"
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#include "util/u_memory.h"
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#include <gelf.h>
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#include <libelf.h>
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#include <sid.h>
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#include <stdio.h>
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#define SPILLED_SGPRS 0x4
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#define SPILLED_VGPRS 0x8
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/* Parse configuration data in .AMDGPU.config section format. */
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void ac_parse_shader_binary_config(const char *data, size_t nbytes, unsigned wave_size,
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const struct radeon_info *info, struct ac_shader_config *conf)
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{
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for (size_t i = 0; i < nbytes; i += 8) {
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unsigned reg = util_le32_to_cpu(*(uint32_t *)(data + i));
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unsigned value = util_le32_to_cpu(*(uint32_t *)(data + i + 4));
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switch (reg) {
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case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
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case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
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case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
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case R_00B848_COMPUTE_PGM_RSRC1:
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case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
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if (wave_size == 32 || info->wave64_vgpr_alloc_granularity == 8)
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conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8);
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else
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conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
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conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
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/* TODO: LLVM doesn't set FLOAT_MODE for non-compute shaders */
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conf->float_mode = G_00B028_FLOAT_MODE(value);
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conf->rsrc1 = value;
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break;
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case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
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conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
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/* TODO: LLVM doesn't set SHARED_VGPR_CNT for all shader types */
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conf->num_shared_vgprs = G_00B02C_SHARED_VGPR_CNT(value);
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conf->rsrc2 = value;
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break;
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case R_00B12C_SPI_SHADER_PGM_RSRC2_VS:
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conf->num_shared_vgprs = G_00B12C_SHARED_VGPR_CNT(value);
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conf->rsrc2 = value;
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break;
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case R_00B22C_SPI_SHADER_PGM_RSRC2_GS:
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conf->num_shared_vgprs = G_00B22C_SHARED_VGPR_CNT(value);
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conf->rsrc2 = value;
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break;
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case R_00B42C_SPI_SHADER_PGM_RSRC2_HS:
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conf->num_shared_vgprs = G_00B42C_SHARED_VGPR_CNT(value);
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conf->rsrc2 = value;
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break;
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case R_00B84C_COMPUTE_PGM_RSRC2:
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conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
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conf->rsrc2 = value;
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break;
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case R_00B8A0_COMPUTE_PGM_RSRC3:
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conf->num_shared_vgprs = G_00B8A0_SHARED_VGPR_CNT(value);
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conf->rsrc3 = value;
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break;
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case R_0286CC_SPI_PS_INPUT_ENA:
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conf->spi_ps_input_ena = value;
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break;
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case R_0286D0_SPI_PS_INPUT_ADDR:
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conf->spi_ps_input_addr = value;
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break;
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case R_0286E8_SPI_TMPRING_SIZE:
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case R_00B860_COMPUTE_TMPRING_SIZE:
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if (info->gfx_level >= GFX11)
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conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(value) * 256;
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else
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conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(value) * 1024;
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break;
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case SPILLED_SGPRS:
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conf->spilled_sgprs = value;
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break;
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case SPILLED_VGPRS:
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conf->spilled_vgprs = value;
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break;
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default: {
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static bool printed;
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if (!printed) {
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fprintf(stderr,
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"Warning: LLVM emitted unknown "
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"config register: 0x%x\n",
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reg);
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printed = true;
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}
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} break;
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}
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}
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if (!conf->spi_ps_input_addr)
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conf->spi_ps_input_addr = conf->spi_ps_input_ena;
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/* GFX 10.3 internally:
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* - aligns VGPRS to 16 for Wave32 and 8 for Wave64
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* - aligns LDS to 1024
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*
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* For shader-db stats, set num_vgprs that the hw actually uses.
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*/
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if (info->gfx_level == GFX10_3) {
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conf->num_vgprs = align(conf->num_vgprs, wave_size == 32 ? 16 : 8);
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}
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/* Enable 64-bit and 16-bit denormals, because there is no performance
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* cost.
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*
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* Don't enable denormals for 32-bit floats, because:
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* - denormals disable output modifiers
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* - denormals break v_mad_f32
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* - GFX6 & GFX7 would be very slow
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*/
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conf->float_mode &= ~V_00B028_FP_ALL_DENORMS;
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conf->float_mode |= V_00B028_FP_64_DENORMS;
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}
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