75 lines
3.6 KiB
ReStructuredText
75 lines
3.6 KiB
ReStructuredText
Hierarchical Depth (HiZ)
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========================
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TODO: Add detailed docs like we have for CCS
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HiZ/stencil on Sandy Bridge
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---------------------------
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Properly enabling HiZ on Sandy Bridge requires certain special considerations.
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From the Sandy Bridge PRM Vol. 2, Pt. 1, 7.5.3 "Hierarchical Depth Buffer" (p.
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312):
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The hierarchical depth buffer does not support the LOD field, it is assumed
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by hardware to be zero. A separate hierarachical depth buffer is required
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for each LOD used, and the corresponding buffer’s state delivered to
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hardware each time a new depth buffer state with modified LOD is delivered.
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The ``3DSTATE_STENCIL_BUFFER`` packet for separate stencil (required for HiZ)
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on sandy bridge also lacks an LOD field. Empirically, the hardware doesn't
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pull the stencil LOD from ``3DSTATE_DEPTH_BUFFER``, it's just always 0 like
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with HiZ.
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As stated in the PRM, this means we need a separate HiZ or stencil buffer for
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each LOD. However, it's not quite as simple as that. If you ignore layered
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rendering, things are pretty straightforward: you need one HiZ surface for each
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main surface slice. With layered rendering, however, we have to be a bit more
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clever because we need a "real" array surface at each LOD. ISL solves this
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with a special miptree layout for layered rendering
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:cpp:enumerator:`isl_dim_layout::ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ` which lays
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out the surface as a miptree of layered images instead of an array of miptrees.
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See the docs for
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:cpp:enumerator:`isl_dim_layout::ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ` for a nice
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description along with an ASCII art diagram of the layout.
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Also, neither ``3DSTATE_STENCIL_BUFFER`` nor ``3DSTATE_HIER_DEPTH_BUFFER`` have
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their own surface dimensions or layout information on Sandy Bridge. They're
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just an address and a surface pitch. Instead, all that other information is
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pulled from ``3DSTATE_DEPTH_BUFFER``. When you combine this with the lack of
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LOD, this means that, technically, we have a full-sized single-LOD stencil or
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HiZ surface at each miplevel of which only the upper left-hand corner of each
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array slice ever gets used. The net effect of this is that, in
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:cpp:enumerator:`isl_dim_layout::ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ`, all LODs
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share the same QPitch even though it's horribly wasteful. This is actually
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pretty convenient for ISL because we only have the one
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:cpp:member:`isl_surf::array_pitch_el_rows` field.
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Due to difficulties with plumbing relocation deltas through ISL's
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depth/stencil/hiz emit interface, we can't handle this all automatically in
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ISL. Instead, it's left up to the driver to do this offsetting. ISL does
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provide helpers for computing the offsets and they work fine with
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:cpp:enumerator:`isl_dim_layout::ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ` so all that's
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really required is to call the ISL helper and add the computed offset to the
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HiZ or stencil buffer address. The following is an excerpt from BLORP where we
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do this as an example:
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.. code-block:: c
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struct blorp_address hiz_address = params->depth.aux_addr;
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#if GFX_VER == 6
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/* Sandy bridge hardware does not technically support mipmapped HiZ.
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* However, we have a special layout that allows us to make it work
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* anyway by manually offsetting to the specified miplevel.
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*/
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assert(info.hiz_surf->dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
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uint32_t offset_B;
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isl_surf_get_image_offset_B_tile_sa(info.hiz_surf,
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info.view->base_level, 0, 0,
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&offset_B, NULL, NULL);
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hiz_address.offset += offset_B;
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#endif
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info.hiz_address =
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blorp_emit_reloc(batch, dw + isl_dev->ds.hiz_offset / 4,
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hiz_address, 0);
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