Commit Graph

139147 Commits

Author SHA1 Message Date
Vinson Lee d6356b81a4 glx: Fix macOS build.
In file included from ../src/glx/apple/apple_glx_context.c:49:
../src/glx/glxclient.h:56:10: fatal error: 'loader.h' file not found
         ^~~~~~~~~~

Fixes: 1cb664c15c ("glx: s/dri_message/glx_message/")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4702
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10568>
2021-05-02 14:16:07 +00:00
Bastian Beranek 960c86d678 glx: Assign unique serial number to GLXBadFBConfig error
Since commit f39fd3dce7 a new GLX error is issued in case context creation
fails. This broke wine on certain hardware: While wine installs an error handler
to ignore this kind of error, it does not function because it expects the
dpy->request serial number of the error to be incremented since the installation
of the handler.

Workaround this by artificially increasing the request number. This also
guarantees a unique serial number for the error.

Fixes: f39fd3dce7
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3969
Signed-off-by: Bastian Beranek <bastian.beischer@rwth-aachen.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10565>
2021-05-02 00:36:03 +00:00
Ilia Mirkin 3326861f4f nv50: add indirect compute support
There's no hardware support for anything indirect, so just read the
parameters out.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin b53b96a86a nv50: add support for doing membars
This requires an address that's safe to read from.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin f451854f39 nv50: add remapping of buffers/images into unified space
This allows us to use up to 15 images or buffers (but not both). GL
supports the concept of combined resource maximums though.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin 58d47ca324 nv50: add compute invocations counter
This is a purely software counter alongside the other hardware counters
for ease of use and consistency. However we have to make room for it in
the allocated query space. Use this opportunity to make the nv50 queries
work like the nvc0 ones in terms of space allocation.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin bd2f14a5ea nv50/ir: add lowering for shared atomics
This is best-effort for pre-nva0 ... works with a single invocation,
i.e. no locking.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin 6b1a526ac5 nv50/ir: add surface op lowering
This handles BUFQ, SUQ, as well as all the various texture types and
formats, driven by data supplied by the driver (and shader itself).

TODO:
 - 2d linear surfaces
 - format via key for writeonly

These will be included in a later change. ES3.1 doesn't require
writeonly, and it's very hard to generate a 2d linear surface.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin 67f98497af nv50: pass surface/buffer parameters to shader via aux buffer
These are needed to implement things like imageSize() as well as feed
data into lowering logic for various access types not handled by the
hardware.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin e762061127 nv50/ir: optimize shift of 0 bits
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin dbdc2b160c nv50/ir: wipe any info about memory when seeing a locking op
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin 1cf864ef9e nv50/ir: mark ATOM as having 3 arguments
Otherwise the final argument doesn't get emitted for CAS in the nv50
emitter.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin 348db055dd nv50/ir: "zero" register does not work with g[] memory
Evidence suggests that having it anywhere, even as a regular e.g. atom
argument, causes issues.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin 21f9b1cbe7 nv50/ir: refine limitation on load/store loading offsets, include atomics
Note that shared memory loads can actually do offsets. The restrictions
vary by generation, this will be added in a later change.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Ilia Mirkin c95d2a86d3 nv50/ir: offset accesses to shared memory
Ideally this should include the size of the inputs as well. This will be
updated when we add support for kernels which take actual inputs.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
2021-05-01 20:04:21 +00:00
Marek Olšák 967757a208 gallium+(u_threaded,r300,r600,radeonsi): move transfer offset into pipe_transfer
Let's use the 4 bytes of unused padding usefully in pipe_transfer.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
2021-05-01 17:38:42 +00:00
Marek Olšák 6005b86893 gallium: remove 4 bytes from pipe_transfer
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
2021-05-01 17:38:42 +00:00
Marek Olšák 00c30dad78 gallium: renumber PIPE_MAP_* enums to remove holes
We could change the type into 16 bits if needed.

PB_USAGE flags need to match PIPE_MAP flags due to static assertions.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
2021-05-01 17:38:42 +00:00
Rob Clark 22575a7b11 freedreno/ci: Update piglit skips/fails
Add spec@arb_pixel_buffer_object@texsubimage cube_map_array pbo to a530
fails for the same reason as spec@arb_texture_cube_map_array@texsubimage cube_map_array
(it is sometimes triggering gpu hangs that cause other flakes).

And remove two a630 xfails that started showing up as UnexpectedPass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
2021-05-01 08:47:50 -07:00
Rob Clark 928453ccb2 freedreno/ci: Mark client_wait_sync_finish as flake
This one has shown up a couple times since fd/go-fast, I'm still trying
to reproduce/debug.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
2021-05-01 08:47:50 -07:00
Rob Clark bc3f66311d freedreno: Flush resources harder
pctx->flush_resource() has the same expectations that the resource can
be shared with an external client as pctx->flush(), but without the
convenience of a fence to know *when* the resource must be visible to
that external client.  So we need to ensure the batch is flushed all the
way to the kernel so that implicit-sync can do it's job.

Fixes: e9a9ac6f77 ("freedreno/drm: Async submit support")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
2021-05-01 08:46:27 -07:00
Rob Clark 5181f40670 freedreno/drm: Allow FD_BO_PREP_FLUSH without _NOSYNC
This provides the upper layer (gallium, etc) a way to ensure that
rendering involving the bo has been flushed all the way to the kernel.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
2021-05-01 08:46:27 -07:00
Rob Clark dbdc979320 freedreno: Remove samples-per-tex tracking
Looks like this was unused, and only served to segfault when unbinding
textures.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
2021-05-01 08:46:27 -07:00
Rob Clark 9fa3312773 freedreno/ci: Isolate dEQP-EGL reset_context tests
To reduce flakes, separate out the dEQP-EGL tests that are intentionally
triggering GPU hangs.  This avoids some kernel side issues with bad
handling of ringbuffer-full scenarios, causing innocent tests to flake.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10560>
2021-05-01 02:37:05 +00:00
Rob Clark cee1673684 ci: Add DEQP_CASELIST_INV_FILTER
Inverts the match compared to DEQP_CASELIST_FILTER

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10560>
2021-05-01 02:37:05 +00:00
Eric Anholt ec7923bd97 ci/freedreno: Mark another recent piglit flake.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10552>
2021-04-30 16:47:09 -07:00
Eric Anholt fc9ba9a911 ci/freedreno: Mark new flakes from the go-fast branch.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10552>
2021-04-30 16:47:02 -07:00
Eric Anholt 0987df6a3e ci/freedreno: Mark dEQP-EGL flakes reported on IRC since its introduction.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10552>
2021-04-30 16:44:20 -07:00
Icecream95 ab8e531cf0 panfrost: Fix viewport scissor for preload draws
The max values are inclusive, so add 1 before aligning. This means
that a max of 32 will be aligned up to 64 then be decremented to 63.

Add a comment to the pan_fb_info struct to document maxx and maxy as
inclusive.

Fixes: 8ba2f9f698 ("panfrost: Create a blitter library to replace the existing preload helpers")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10542>
2021-04-30 22:24:58 +00:00
Icecream95 9910a14a1a panfrost: Remove incorrect comment
The comment was wrong in its original location and is wrong here, just
remove it.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10542>
2021-04-30 22:24:58 +00:00
Dylan Baker f03da01fe3 meson/vulkan: fix linkage on windows
The current approach likley breaks icl and clang-cl, but it seems that
the problem isn't even really related to MSVC, but to Meson's Visual
Studio backend, as such, let's use link-whole unless we're using a
Visual Studio backend.

Fixes: 48d31a6280
       ("meson: link vulkan_util with link_whole on mingw")

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: James Park <jpark37@lagfreegames.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10506>
2021-04-30 18:49:20 +00:00
Gustavo Padovan d47c2af8d2 gitlab-ci: enable all 3 intel devices as manual in MR pipelines
This uses the rule created by .test-manual-mr that enables experimental
devices in MR pipelines, but not for Marge.

The goal is to expose the devices to more possibility of testing before
we enable them automatically.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10405>
2021-04-30 17:15:06 +00:00
Gustavo Padovan c5e06bb894 gitlab-ci: rule anchor for experimental devices as manual in MRs
We want to give developers the option to run their jobs on devices
that are still being stabilized in the CI infrastructure.

These jobs should be optional and not prevent merging from happening.

The is-forked-branch-or-pre-merge anchor was not being used anywhere,
so it was changed to is-forked-branch-or-pre-merge-not-for-marge to
create this new rule.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10405>
2021-04-30 17:15:06 +00:00
Jason Ekstrand b80720acb1 intel/isl: Fix isl_color_value_unpack to match the prototype
The prototype uses a pointer and the actual function definition had an
array.  For some reason, GCC never complained about this until GCC 11.
This fixes a compile warning when building with GCC 11.

Fixes: 09ced65420 "intel/isl: Add format conversion code"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10537>
2021-04-30 17:01:05 +00:00
Danylo Piliaiev 1201aa9332 ir3: do not move varying inputs that depend on unmovable instrs
Not all varying fetches could be pulled into the start block.
If there are fetches we couldn't pull, like load_interpolated_input
with offset which depends on a non-reorderable ssbo load or on a
phi node, this pass is skipped since it would be hard to find a place
to set (ei) flag (beside at the very end).

We also don't have to manually set (ei) in such cases since a5xx and
a6xx do automatically release varying storage at the end.
Earlier gens need further testing, however they do not support
interpolateAt* functions at moment, so unless we would like to support
sample shading on them - they are fine.

Fixes crash in GTA V.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10483>
2021-04-30 14:49:18 +00:00
Martin Peres 5d5f7c79a5 ci: add the dEQP expectations for radv on Renoir
This patch should not be backported directly to 21.1, as master already
fixed one failure. I'll post a backport of this series with the
additional failure documented when this one gets merged.

v2:
 - remove dEQP-VK.synchronization.* from the skip list (Hakzsam)
 - drop dEQP-VK.memory.pipeline_barrier.* from the skip list (Hakzsam, me)

v3:
 - re-introduce dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.1048576

Signed-off-by: Martin Peres <martin.peres@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10539>
2021-04-30 16:53:39 +03:00
Erik Faye-Lund 91727182dc zink: also enable float16 from KHR extension
This allows us to use 16 bit floats on pre Vulkan 1.2 drivers as well.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund 8966029f95 zink/codegen: prefer first definition of prop/feature structs
Some extensions have renamed their property and/or feature structs,
listing the "correct" type first. So we should prefer that one rather
than overwriting it with a later one.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund b59b42ec5e zink: enable 16-bit float support
This finally enables the 16-bit float feature.

Ideally we would also check VK_KHR_shader_float16_int8, but the python
code for that is giving me some issues now, so let's deal with that
later.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund 903b6af298 zink: perform fp16 texture-lookups as fp32 and then convert
SPIR-V doesn't seem to have any opcodes to sample textures using lower
precision directly, so let's sample and downcast later instead.

Ideally, we'd do this as a NIR-pass first, but this does the trick for
now.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund 1971efe5ba zink: support emitting 16-bit float types
This prepares us for being able to support using 16-bit float types
in shaders, which might help performance in some cases.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund 404521529c zink: enable 16-bit int support
The mysterious support_16bit_int_alu-option doesn't really mean what it
says. Instead it means "we support 16 bit compares, if 16 bit ALU
operations occur". And since 16 bit operations only appear if we're
lowering mediump/lowp, we can always set this option.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund 0b45dbea13 zink: support emitting 16-bit int types
This prepares us for being able to support using 16-bit int types in
shaders, which might help performance in some cases.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund 6f2d6b9d4f zink: always lower function-temp derefs
We're about to need this in order to support 16-bit floats, because the
lowering code for that emits function-temp derefs, and we don't handle
it.

A better long-term solution would be to just support function-temp
variables and indirect derefs. But that's more work, and kinda
orthogonal to what this patchset tries to accomplish, so let's save that
for another day.

Fixes the following piglit:
- spec@arb_gl_spirv@execution@ubo@array-inside-ubo-copy

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund 3f4eacb38a zink: run nir_opt_algebraic_late
This pass is needed to finish off the [ui]2imp lowering. Follow what
other drivers do and perform some dead-code elimimation etc when
lowering happens.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund 204cd1b893 zink: respect bit-size of dref-result
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Erik Faye-Lund ab1fc9e32c zink: use UINT32_MAX instead of UINT_MAX
This is a 32-bit argument, so on platforms where UINT_MAX is larger,
this is going to... well, do exactly the same thing, but this is
slightly clearer why.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
2021-04-30 12:02:04 +00:00
Icecream95 f85b7aa5d4 pan/mdg: Fix calculation of available work registers
Make the rmu variable signed; otherwise the MAX2 has no effect and
work_count can end up being larger than 16.

Fixes INSTR_OPERAND_FAULTs in SuperTuxKart.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4707
Fixes: c6ed8bf77c ("panfrost: Fix uniform_count on Midgard")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10507>
2021-04-30 10:38:35 +00:00
Jordan Justen 3f04383521 intel/compiler: Fix INTEL_DEBUG=hex
With the missing else, this prints the compacted hex followed by hex
for an uncompacted version of the compacted instruction. It also
doesn't print hex for instructions that are not compacted.

Fixes: bc4a127d6e ("intel/disasm: Label support in shader disassembly for UIP/JIP")
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10535>
2021-04-30 01:51:23 -07:00
Jose Maria Casanova Crespo ab1d66a111 ci/v3d: Update piglit expectations.
As piglit job is manual, I forgot to update three new test passing at
spec@ext_image_dma_buf_import subgroup after merging
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10524

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10536>
2021-04-30 10:22:53 +02:00