Commit Graph

11 Commits

Author SHA1 Message Date
Bas Nieuwenhuizen 469341fabc radv: Add modifier fails for CTS bug.
Fixes: 58e5232625 ("radv: Enable DRM format modifiers on GFX9+.")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8828>
2021-02-03 16:18:20 +00:00
Rhys Perry 56cd79b63d radv: round-up num_records division in radv_flush_vertex_descriptors
Vertex attribute bounds checking is supposed to be done per-attribute:
   is_oob = index * stride + attrib_offset + attrib_size > buffer_size
but we were obtaining num_records by dividing the buffer size by the
stride, making it per-vertex:
   is_oob = index * stride + (stride - 1) >= buffer_size

An example from Dead Cells (Wine) is:
attribute bindings: 0, 1, 2
attribute formats: r32g32, r32g32, r32g32b32a32
attribute offsets: 0, 0, 0
binding buffers: all the same buffer
binding offsets: 0, 8, 16
binding sizes: 128, 120, 112
binding strides: 32, 32, 32

Workaround this issue without switching to per-attribute descriptors by
rounding up the division. This is still incorrect, but it should now no
longer consider in-bounds attributes out-of-bounds.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3796
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4199
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8835>
2021-02-03 09:53:08 +00:00
Samuel Pitoiset 2d0c723ce6 radv: make sure FMASK compression is enabled for MSAA copies
Fixes dEQP-VK.api.copy_and_blit.*.4_bit. I think the MSAA2x and
MSAA8x just passed by luck.

Fixes: 7b21ce401f ("radv: disable FMASK compression when drawing with GENERAL layout")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7915>
2020-12-23 11:25:34 +00:00
Samuel Pitoiset 6925c031e0 ci: update the list of expected failures for RADV
Against vulkan-cts-1.2.4.1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7626>
2020-11-15 16:49:47 +00:00
Eric Anholt bf29daa1b5 ci/deqp: Switch to a new dEQP runner written in Rust.
I found the C++ runner hard to develop on, and we had stability issues and
outstanding feature needs that made me want something I felt good about
hacking on.  Thus, Rewrite It In Rust of the deqp runner.

The new runner includes:

- Skip lists don't reshuffle the test list.
- Known-flake handling without resorting to skip lists (fixing our main CI
  reliability issue on a3xx right now).
- Per-thread Vulkan shader caches should speed up VK CI runtime.
- Tracking of crashes separate from fails (so we can see progress on that
  front).
- Logging of deqp stderr spam (particularly assertion failures!) in the CI
  log.
- Integrated QPA filtering so we don't have bash perf issues for it.
- Logging of what caselist to go look at for a given error report (in red,
  so it's easier to find in your CI log).
- The code is 1/3 unit tests, and easy to extend for more coverage.
- Non-LAVA CI runs create a failures.csv in artifacts that you can check
  in as your deqp-*-fails.txt file.
- Test runtime is included in results.csv so you can debug how to speed up
  your CI job.
- Pretty summary at the end of the run of slow/flaky/failed tests.

Since this is a new runner with a different RNG, the test groups are
shuffled one more time.  This seems to result in some panfrost T720
stability issues (See its new deqp-panfrost-t720-flakes.txt), and one new
flake in freedreno a630.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7434>
2020-11-06 19:48:39 +00:00
Rhys Perry fdadbdb513 radv: remove descriptor_indexing fails from expected fails
I think these should be fixed since
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6451. They also
pass for me on polaris and navi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6586>
2020-09-03 18:51:33 +00:00
Bas Nieuwenhuizen 371f6f42ad radv: Update CI expectations for the recent descriptor indexing regressions.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6285>
2020-08-12 11:15:42 +00:00
Rhys Perry d169f09e37 aco: be more careful combining additions that could wrap into loads/stores
SMEM does the addition with 64-bits, not 32. So if the original code
relied on wrapping around (for example, for subtraction), it would break.

Apparently swizzled MUBUF accesses also have issues with combining
additions that could overflow. Normal MUBUF accesses seem fine.

fossil-db (Navi):
Totals from 27219 (20.02% of 135946) affected shaders:
CodeSize: 128303256 -> 131062756 (+2.15%); split: -0.00%, +2.15%
Instrs: 24818911 -> 25280558 (+1.86%); split: -0.01%, +1.87%
VMEM: 162311926 -> 177226874 (+9.19%); split: +9.36%, -0.17%
SMEM: 18182559 -> 20218734 (+11.20%); split: +11.53%, -0.34%
VClause: 423635 -> 424398 (+0.18%); split: -0.02%, +0.20%
SClause: 865384 -> 1104986 (+27.69%); split: -0.00%, +27.69%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2748
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2720>
2020-07-21 18:25:35 +00:00
Rhys Perry fac813dc61 spirv: don't split memory barriers
If the SPIR-V had a shared+image memory barrier, we would emit two NIR
barriers: a shared barrier and an image barrier.

Unlike a single barrier, two barriers allows transformations such as:

intrinsic image_deref_store (ssa_27, ssa_33, ssa_34, ssa_32, ssa_25) (1)
intrinsic memory_barrier_shared () ()
intrinsic memory_barrier_image () ()
intrinsic store_shared (ssa_35, ssa_24) (0, 1, 4, 0)
->
intrinsic memory_barrier_shared () ()
intrinsic store_shared (ssa_35, ssa_24) (0, 1, 4, 0)
intrinsic image_deref_store (ssa_27, ssa_33, ssa_34, ssa_32, ssa_25) (1)
intrinsic memory_barrier_image () ()

This commit fixes two dEQP-VK.memory_model.* CTS tests with ACO.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5951>
2020-07-20 12:05:16 +00:00
Samuel Pitoiset 11a6a96f8a radv: fix wide lines with multisample enabled
When set, EXPAND_LINE_WIDTH expands the line width by 1/cos(a),
where a is the minimum angle from horizontal or vertical. This
seems required by OpenGL line rasterization but not by Vulkan.

Similar to what AMDVLK and AMDGPU-PRO do for AA wide lines.

This fixes
dEQP-VK.rasterization.interpolation_multisample_*_bit.*lines_wide.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5698>
2020-07-02 07:51:48 +00:00
Samuel Pitoiset 7e98f2534c gitlab-ci: add a list of expected failures for RADV/ACO on NAVI14
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5647>
2020-06-25 14:15:49 +00:00