It's only used by buffers and only zink uses it privately for textures too.
This is part of removing u_resource_vtbl.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10659>
This is the initial step towards removing u_resource_vtbl.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10659>
State uploads are bound to the batch, so if the batch changes, we
invalidate all state. Theoretically this isn't totally optimal but in
practice it should be good enough.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10888>
This patch will avoid reallocation,if surface is already protected.
Fixing the comparision logic of boolean value(true \ flase) with
PIPE_BIND_PROTECTED.
Fixes: 81be8b3c2f ("va/picture: make sure destination buffer is protected if needed")
Signed-off-by: SureshGuttula <suresh.guttula@amd.corp-partner.google.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10916>
this was broken for the indirect case if the indirect draw count or
firstIndex was nonzero and also would rewrite the index buffer onto the
wrong offset of the dst buffer
Fixes: 0c85d6c523 ("gallium/util: factor out primitive-restart rewriting logic")
Fixes: 330d0607ed ("gallium: remove pipe_index_buffer and set_index_buffer")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10909>
The wayland EGL platform sets the modifier count to 0 in some cases
to signal that modifiers should not be used, even if a list of modifiers
is present. The loader_dri_create_image helper didn't handle this case
properly and called the modifierful driver interface with a 0 modifier
count, leading to the obvious outcome of the driver being unable to
allocate an image.
Fixes: cb9ae4273d ("dri: add loader_dri_create_image helper")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10903>
SCS_ONE and ISL_CHANNEL_SELECT_ONE (and SCS_ZERO and
ISL_CHANNEL_SELECT_ZERO) have the same values, so this doesn't matter in
practice. However, some compiler warning options will cause warnings to
be generated.
src/gallium/drivers/iris/iris_state.c: In function ‘fmt_swizzle’:
src/gallium/drivers/iris/iris_state.c:2177:32: warning: implicit conversion from ‘enum GFX125_ShaderChannelSelect’ to ‘enum isl_channel_select’ [-Wenum-conversion]
2177 | case PIPE_SWIZZLE_1: return SCS_ONE;
| ^~~~~~~
src/gallium/drivers/iris/iris_state.c:2178:32: warning: implicit conversion from ‘enum GFX125_ShaderChannelSelect’ to ‘enum isl_channel_select’ [-Wenum-conversion]
2178 | case PIPE_SWIZZLE_0: return SCS_ZERO;
| ^~~~~~~~
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
These aren't real formats. They cannot be used with
RenderbufferObjects, Textures, or anything else visible through the GL
API. The only purpose is to support YUYV textures imported through
EGL_image_external. There is hardware that can sample from this
subsampled format, but the hardware does not do the colorspace
conversion automatically.
v2: Treat these formats as compressed. This is a lie, but it seems to
be a less egregious lie than what I was doing before. It also passes
'ninja test'.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
v2: Add all the Y21x tests to the A530 expected fail list. All of the
YUV image import tests fail on this platform, and nobody has been able
to investigate why.
v3: Update the comment describing the zeroed bits in Y212. Suggested by
Emma.
v4: Add all Y21x test to the rpi3 expected fail list.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
v2: Don't leak __DRI_IMAGE_FOURCC_RGBA16161616 to applications.
v3: Fix typo in __DRI_IMAGE_FOURCC_RGBA16161616 table entry.
v4: Add the Y412 and Y416 tests to the A530 expected fail list. Many
YUV image import tests fail on this platform, and nobody has been able
to investigate why.
v5: Update the comment describing the zeroed bits in Y412. Suggested by
Emma.
v6: Add all Y41x test to the rpi3 expected fail list.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
These are similar to AYUV, but the channel ordering is different... in
such a way that there's no RGBA format that will make the channels line
up right.
v2: Rebase on bc438c91d9 ("nir/lower_tex: ignore texture_index if
tex_instr has deref src")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
All of these formats, and ones that will be added later in this series,
are in the copy of drm_fourcc.h in drm-uapi.
Suggested-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
s/are may be/might be/
Also add a missing comma.
v2: Also s/its/it's/. Suggested by Nanley.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with PIPE_BIND_SCANOUT set,
which we can't support. That led to crashes later when we tried to
create such an image, and isl rightly denied it.
Fixes crashes in wflinfo since c03e79d783, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes: c03e79d783 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with __DRI_IMAGE_USE_SCANOUT
set, which we can't support. That led to crashes later when we tried
to create such an image, and isl rightly denied it.
This duplicates a bit of code from ISL, but the isl_gfx6_filter_tiling
function that we ought to use to filter things relies on surf_info,
which we don't have at this stage. This is probably good enough.
Fixes crashes in wflinfo since c03e79d783, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes: c03e79d783 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
In the case where we're rendering on the Intel GPU, but displaying
on an AMD and NVIDIA GPU, we need to follow their pitch requirements
for our linear scanout buffers.
Based on a patch by Lionel Landwerlin.
Closes: #4706
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10895>
The swizzle() requires a proper ureg with the 0/1 swizzle fields filled
in, or our ONE swizzles end up reading .x instead. This meant that we
were killing based on the incoming value of R0.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
This hardware can't do any form of indirect addressing. The couple of new
Crashes are the backend falling over when faced with loops/ifs.
Fixes: 8a22064d31 ("i915g: Implement vertex textures.")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
The DIFFUSE thing would write an undefined result if the shader that
failed to compile didn't read VARYING_SLOT_COL0, causing flakes in CI.
This does make 2 piglit tests that were expecting red spuriously pass.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
The 3D-pipeline fast clears try to emit FS constants before an FS is
necessarily bound, causing segfaults in dEQP. Plus it flushes the whole
batchbuffer so it'll probably be slower anyway.
Fixes: 6358e6371b ("i915g: implement hw clear")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Marek Olšák
Mike Blumenkrantz
Rob Clark
Juan A. Suarez Romero
Alyssa Rosenzweig
SureshGuttula
Lucas Stach
Timothy Arceri
Ian Romanick
Kenneth Graunke
Andres Gomez
Emma Anholt
Eric Anholt